Table of Contents
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1
2
D
U
1
D
V
1
R
2
7
V
C
C
_
0
0
7
2
1
V
C
C
_
0
2
1
4
2
V
C
C
_
0
4
2
7
4
V
C
C
_
0
7
4
1
1
1
V
C
C
_
1
1
1
1
2
1
V
C
C
_
1
2
1
1
4
3
V
C
C
_
1
4
3
9
V
S
S
_
0
0
9
2
3
V
S
S
_
0
2
3
4
4
V
S
S
_
0
4
4
7
7
V
S
S
_
0
7
7
1
0
9
V
S
S
_
1
0
9
1
1
8
V
S
S
_
1
1
8
C
1
4
5
V
S
S
_
1
4
5
V
1
R
2
8
5
P
L
L
V
C
C
_
0
8
5
C
2
9
8
8
V
S
S
_
0
8
8
0
1 .
u
B /
1
6
V
3
R
3
1
0
4
A
V
R
E
F
_
1
0
4
1
0
2
A
V
C
C
_
1
0
2
C
3
0
1
0
3
A
V
S
S
_
1
0
3
0
1 .
u
B /
1
6
V
3
R
3
1
8
1
U
S
B
A
P
V
C
C
_
1
8
B
C
1
8
3
C
3
2
0
0 .
1
u
B /
1
6
0
1 .
u
B /
1
6
1
8
0
U
S
B
A
P
V
S
S
_
1
8
V
1
R
2
1
8
2
U
S
B
A
V
C
C
_
1
8
2
C
1
8
4
C
1
8
8
C
3
3
0
0 .
1
u
B /
1
6
4
7 .
u
F
B /
1
0
0
1 .
u
B /
1
6
1
8
3
U
S
B
A
V
S
S
_
1
8
3
1
7
9
R
E
F
R
N I
_
1
7
9
R
2
0
R
7
S
7
2
1
0
2
5
6 .
k
1 /
%
A
1
2
SA Main PCB (3/12) [CPU (2)]
3
V
3
R
1
1
P
V
C
C
_
0
1
1
2
5
P
V
C
C
_
0
2
5
3
6
P
V
C
C
_
0
3
6
4
7
P
V
C
C
_
0
4
7
5
8
P
V
C
C
_
0
5
8
6
7
P
V
C
C
_
0
6
7
7
8
P
V
C
C
_
0
7
8
9
3
P
V
C
C
_
0
9
3
1
0
6
P
V
C
C
_
1
0
6
1
2
5
P
V
C
C
_
1
2
5
1
3
0
P
V
C
C
_
1
3
0
1
3
6
P
V
C
C
_
1
3
6
1
4
7
P
V
C
C
_
1
4
7
1
9
5
P
V
C
C
_
1
9
5
2
0
6
P
V
C
C
_
2
0
6
1
8
V
S
S
_
0
1
8
3
4
V
S
S
_
0
3
4
3
9
V
S
S
_
0
3
9
5
4
V
S
S
_
0
5
4
6
5
V
S
S
_
0
6
5
8
9
V
S
S
_
0
8
9
9
1
V
S
S
_
0
9
1
1
2
3
V
S
S
_
1
2
3
1
2
8
V
S
S
_
1
2
8
1
3
4
V
S
S
_
1
3
4
1
4
0
V
S
S
_
1
4
0
1
6
2
V
S
S
_
1
6
2
1
8
6
V
S
S
_
1
8
6
1
8
7
V
S
S
_
1
8
7
1
9
3
V
S
S
_
1
9
3
2
0
3
V
S
S
_
2
0
3
V
1
R
2
V
3
R
3
1
6
5
1
U
S
B
D
P
V
C
C
_
1
6
5
1
7
2
U
S
B
D
P
V
C
C
_
1
7
2
1
7
0
U
S
B
D
V
C
C
_
1
7
0
1
7
7
0
U
S
B
D
V
C
C
_
1
7
7
1
8
4
U
S
B
U
V
C
C
_
1
8
4
1
8
5
U
S
B
U
V
S
S
_
1
8
5
1
7
8
U
S
B
D
V
S
S
_
1
7
8
1
7
1
U
S
B
D
V
S
S
_
1
7
1
1
7
3
U
S
B
D
P
V
S
S
_
1
7
3
1
6
6
U
S
B
D
P
V
S
S
_
1
6
6
3
4
5
3
T
1
2
4
R
1
3
1
M
T
1
2
6
X
1
R
1
4
F
C
X
0 -
6
_
4
8
M
H
z
T
1
2
9
4
7
0
R
1
5
T
1
3
3
T
1
3
2
4
7
k
C
8
C
9
7
p
C /
H
5
0
7
p
C /
H
5
0
V
3
R
3
U
2
R
1
6
V
3
R
3
1
0
k
1
4
R
1
V
N I
O
U
T
C
2
6
C
2
7
0
1 .
u
B /
1
6
2
3
T
1
3
6
1
0
0
0
p
B /
V
S
S
C
d
C
2
8
X
C
6
1
1
9
N
2
8
A
N
R
-
G
0
0 .
2
2
u
B /
1
6
U
1
C
1
1
7
T
C
K
1
1
3
T
R
S
T
1
1
4
J
P
0
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1
T /
D
O
1
1
6
T
M
S
1
1
5
J
P
0
_
0
T /
I D
R
7
S
7
2
1
0
2
4
5
6-5
6
U
1
B
L
1
2
R
1
2
8
6
4
5
E
X
T
A
L
C
I K
O
8
7
1
3
0
1 /
%
X
T
A
L
B
L
M
1
5
B
C
1
0
7
A
U
I D
O
_
X
1
1
0
8
A
U
I D
O
_
X
2
8
3
R
T
C
X
1
8
4
R
T
C
X
2
1
6
3
1
7
6
T
1
2
5
U
S
B
_
X
1
V
B
U
S
N I
0
1
6
4
1
7
5
U
S
B
_
X
2
D
P
0
1
7
4
D
M
0
1
0
5
1
6
9
T
1
3
0
B
S
C
A
N
P
V
B
U
S
N I
1
1
6
8
D
P
1
9
2
1
6
7
n
R
S
T
D
M
1
R
7
S
7
2
1
0
2
7
1
k
T
1
3
5
5
0
V
3
R
3
R
A
5
C
3
1
1
0
k
0
1 .
u
B /
1
6
T
1
3
7
T
1
3
8
T
1
3
9
T
1
4
1
T
1
4
2
R
1
8
R
1
9
0
1
0
0
k
3
5 ,
n
R
S
T
V
3
Title
MAIN PCB / CPU (2) (3/12)
Size
Number
PPS00152-**, PPS00218-**
A4
Date:
File:
6
Chapter 6. Circuit Diagrams
7
8
T
1
2
3
B
U
S
C
L
K
4
5 ,
1
2
1
D
U
S
B
V
B
U
S
0
1
0
U
S
B
D
P
0
1
0
U
S
B
D
M
0
1
0
U
S
B
V
B
U
S
1
8
U
S
B
D
P
1
8
U
S
B
D
M
1
8
n
R
S
T
V
3
3
5 ,
C
V
3
R
3
J
1
1
+3.3V
TMS
JTAG ConnectorS
2
3
GND
01: +3.3V
02: TMS
4
TCK
03: GND
04: TCK
B
5
GND
05: GND
06: TDO
6
TDO
07: NC
08: TDI
7
NC
09: GND
10: nRES
8
TDI
9
GND
1
0
nRES
( "
N
A
" )
ARM JTAG
A
Revision
A
Sheet
of
Drawn By:
7
8
CL-E720DT
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