Integra DTR-4.9 Service Manual page 64

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-29
Q8051 : SiI9013 ( HDMI Receiver)-4/4
TERMINAL DESCRIPTION
Configuration / Programming Pins
Pin Name Pin #
INT 91
RESET# 89
DSCL 42
DSDA 41
CSCL 40
CSDA 39
SCDT 90
CI2CA 38
PWR5V 44
RSVDL 88
RSVD 48
NC 43
Differential Signal Data Pins
Pin Name Pin #
RXC+ 51
RXC- 50
RX0+ 55
RX0- 54
RX1+ 59
RX1- 58
RX2+ 63
RX2- 62
Power and Ground Pins
Pin Name Pin #
CVCC18 12, 24, 36, 45, 81, 112, 125
CGND 13, 25, 37, 80, 113, 126
IOVCC 7, 19, 31, 68, 77, 98, 107, 120
IOGND 6, 18, 30, 69, 78, 97, 106, 118
AVCC 49, 53, 57, 61
AGND 52, 56, 60, 64
PVCC 47
PGND 46
AUDPVCC18 82
AUDPGND 83
DVCC18 66
65
DGND
XTALVCC 86
REGVCC 87
Dir Description
Output Interrupt Output.
Input Reset Pin. Active LOW. Note that this pin must be dynamically controlled as
part of normal operation. This is typically done by the host processor.
2
Input DDCI C Clock for DDC.
2
Bi-Di DDCI C Clock for DDC.
2
Input Configuration I C Clock.
2
Bi-Di Configuration I C Data.
Output Indicates active video at HDMI input port.
2
Input I C Device Address Select.
Input TMDS Port Transmitter Detect.
Input Reserved, must be tied LOW.
--- Reserved Pin, leave unconnected.
--- No connect.
Dir Description
Input TMDS input clock pair.
Input
Input TMDS input data pair.
Input
Input TMDS input data pair.
Input
Input TMDS input data pair.
Input
Type
Power
Ground
Power
Ground
Power
Ground
Power
Ground
Power
Ground
Power
Ground
Power
Power
Description
Digital Logic VCC (1.8V)
Digital Logic GND
Input / Output Pin VCC (3.3V)
Input / Output Pin GND
TMDS Analog VCC (3.3V)
TMDS Analog GND
TMDS PLL VCC (3.3V)
TMDS PLL GND
ACR PLL VCC (1.8V)
ACR PLL GND
ACR PLL Digital VCC (1.8V)
ACR PLL GND
ACR PLL Crystal Input VCC (3.3V)
ACR PLL Regulator VCC (3.3V)
DTR-4.9