Integra DTR-4.9 Service Manual page 59

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-24
Q8401 : SiI9034CTU (HDMI Transmitter)-3/4
TERMINAL DESCRIPTION
Video and Audio Input pins
Pin Name Pin #
D0 94
D1 93
D2 92
D3 91
D4 90
D5 86
D6 85
D7 84
D8 79
D9 78
D10 77
D11 75
D12 74
D13 73
D14 72
D15 71
D16 63
D17 62
D18 61
D19 60
D20 59
D21 58
D22 57
D23 56
88
IDCK
DE 1
HSYNC 2
VSYNC 3
SCK 11
WS 10
SD0 9
SD1 8
SD2 7
SD3 6
DL0 17
DR0 16
DL1 19
DR1 18
DL2 21
DR2 20
DL3 23
DR3 22
DCLK 15
MCLK 5
SPDIF 4
Dir Description
Input These are the lower 12 bits of the 24-bit pixel bus.
Input These pins are highly configurable, and support multiple RGB and YCbCr formats.
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input These are the upper 12 bits of the 24-bit pixel bus.
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input Input Data clock
Input Data enable
Input Horizontal Sync input control signal
Input Vertical Sync input control signal
2
Input I S Serial Clock
2
Input I S Word Select
2
Input I S Serial data
2
Input I S Serial data
2
Input I S Serial data
2
Input I S Serial data
Input One-bit Audio data Left 0
Input One-bit Audio data Right 0
Input One-bit Audio data Left 1
Input One-bit Audio data Right 1
One-bit Audio data Left 2
Input
Input One-bit Audio data Right 2
Input One-bit Audio data Left 3
Input One-bit Audio data Right 3
Input One-bit Audio Clock Input
Input Audio Input Master Clock
Input S/PDIF Audio Input.
DTR-4.9