Integra DTR-4.9 Service Manual page 63

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-28
Q8051 : SiI9013 ( HDMI Receiver)-3/4
TERMINAL DESCRIPTION
Digital video Output Pins
Pin Name Pin # Dir
QE0 124 Output
QE1 123 Output
QE2 122 Output
QE3 121 Output
QE4 117 Output
QE5 116 Output
QE6 115 Output
QE7 114 Output
QE8 111 Output
QE9 110 Output
QE10 109 Output
QE11 108 Output
QE12 105 Output
QE13 104 Output
QE14 103 Output
QE15 102 Output
QE16 101 Output
QE17 100 Output
QE18 99 Output
QE19 96 Output
QE20 95 Output
QE21 94 Output
QE22 93 Output
QE23 92 Output
Digital Audio Output Pins
Pin Name Pin #
XTALIN 85
84
XTALOUT
MCLK 79
SCK 76
WS 75
SD0 74
SD1 73
SD2 72
SD3 71
SPDIF 70
MUTE 67
Description
24-Bit Even Pixel
Dir Description
Input Crystal Clock Input.
Output Crystal Clock Output.
Bi-Di Audio Master Clock Input Reference.
2
Output I S Serial Clock Output.
2
Output I S Word Select Output.
2
Output I S Serial Data Output.
2
Output I S Serial Data Output.
2
Output I S Serial Data Output.
2
Output I S Serial Data Output.
Output S/PDIF Audio Output.
Output Mute Audio Output.
Pin Name Pin # Dir
QO0 35 Output
QO1 34 Output
QO2 33 Output
QO3 32 Output
QO4 29 Output
QO5 28 Output
QO6 27 Output
QO7 26 Output
QO8 23 Output
QO9 22 Output
QO10 21 Output
QO11 20 Output
QO12 17 Output
QO13 16 Output
QO14 15 Output
QO15 14 Output
QO16 11 Output
QO17 10 Output
QO18 9 Output
QO19 8 Output
QO20 5 Output
QO21 4 Output
QO22 3 Output
QO23 2 Output
127 Output
DE
HSYNC 128 Output
VSYNC 1 Output
ODCK 119 Output
DTR-4.9
Description
24-Bit Odd Pixel
Data enable
Horizontal Sync.
Vertical Sync.
Output Data Clock