Pod Clock Field (State Only) - HP 16550A User Reference

100-mhz state/500-mhz timing logic analyzer
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Pod Clock Field (State only)

Pod Clock Field (State only)
The Pod Clock field identifies the type of clock arrangement assigned to each
pod. When the Pod Clock field is selected, a clock arrangement type menu
appears with the choices of Master, Slave, or Demultiplex. Once a pod clock
is assigned a clock arrangement, its identity and function follows what is
configured in the Master and Slave Clock fields. The Pod Clock field and the
clocking arrangement is only available in a state analyzer.
Master
This option specifies that data on all pods designated "Master Clock", in the
same analyzer, are strobed into memory when the status of the clock lines
match the clocking arrangement specified under the Master Clock.
See Also
The "Master and Slave Clock Field" found later in this chapter for information
about configuring a clocking arrangement.
The "Type Field" in the Configuration menu chapter for information on
selecting analyzer types.
Arrangement type selection menu
Pod clock field
Pod Clock Field
4–15

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