Troubleshooting The Digital Kernel - Fluke 39 Service Manual

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Service Manual
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Troubleshooting the Digital Kernel

To isolate a problem within the Digital Kernel, proceed as follows:
1. Check for loose or unsoldered pins on U2 through U7.
2. Check all VCC pins on U2 for 3.3V. Because the VCC pins on the DSP supply
3. Check that CKSUM_OK (U2-17) makes a transition from low to high in less than
4. Check that W_DOG (U2-35 or the side of C57 not tied to R77) changes state at least
5. Check the DSP CLOCK signal (U2-123 or U3-43) with a high-speed oscilloscope. A
6. The reset line (U2-125) should go high approximately 20 ms after the DSP chip sees
7. Check that MODE C (U2-119) is low when reset* (U2-125) goes from low to high.
8. Check that MODE B (U2-120) is low when reset* (U2-125) goes from low to high.
9. Check that MODE A (U2-121) is high when reset* (U2-125) goes from low to high.
10. Check for activity on the CS_SRAM* and CS_BOOTROM* lines. When the DSP
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power to different areas of the chip, any VCC pin that does not receive 3.3V when o
is pressed could prevent the DSP from powering up.
150 ms when o is pressed or when the power supply is up to 3.3V. A checksum line
that fails to make this transition indicates the program was not loaded properly from
the EPROM into SRAM. This could indicate a problem with an address line, data
line, control line (RD, WR, DS, PS, x/y) or EE_UPLOW line that is not high at reset,
or it could indicate that U2 through U7 is faulty or has a bad solder joint.
once every second. For certain areas of code, such as in the user interface, it may
change state at a significantly higher rate. The minimum width of the a W_DOG
pulse is 15µsec. If the W_DOG signal does not appear and the DSP is running with
the CKSUM_OK line high, then U2 may be bad.
clock frequency of 38.6918 MHz should be observed. If this clock signal is not
present, verify that the oscillator circuit tied to U2-1 and U2-132 is correct. The
crystal frequency is 3.86918 MHz. The DSP chip multiplies the crystal frequency by
10 to produce the DSP clock frequency.
3.3V on its Vcc pins. If this does not occur, check the power supply and the reset
circuit.
If it is not low, check that diode CR2 is correct and installed properly.
If it is not low, check that diode CR3 is correct and installed properly.
If it is not high, check that IRQA is pulled high and U3-9 is not driving IRQA low. If
U3 is driving IRQA low when reset* is active, verify that the reset line to U3-2 is
high when reset* is active. If U3-2 is high while reset* is active and U3 is still
driving IRQA low, then U3 may be bad.
reset line is released, the DSP should start reading 1536 bytes starting at boot ROM
address p:$C000. On power up, the DSP is set to 15 wait states for all memory
locations; thus, CS_BOOTROM* is asserted low and should have a width of
approximately 450 ns. Next, there should be a short pause (a few milliseconds) as
the DSP executes the loaded code. Finally, the DSP copies all code from boot ROM
to SRAM. Since the first 512 words of SRAM is onchip, no external SRAM activity
will be observed until the onchip SRAM is full. While copying the remaining code
to external SRAM, CS_BOOTROM* should be an active low pulse of
approximately 310 ns when reading from the EPROM, and CS_SRAM* should be
an active low pulse of approximately 70 ns when writing to external SRAM. The
timing of the signals associated with reading the boot ROM or reading/writing to the
SRAM should be compared with the following timing diagrams.