Vee; Vdd; Vss; Vref - Fluke 39 Service Manual

output to 3.3V dc ±5%. The feedback voltage is ≈1.224V dc. Transformer T1 and
capacitor C63 filter the output of U30. U30 has an internal Undervoltage Lockout circuit.
The circuit monitors the supply voltage and allows normal operation for voltages greater
than 3.75V dc (typical) with 0.25V dc of hysteresis. When an undervoltage is detected,
control logic turns off the internal power FET and momentarily grounds C50. This starts
a soft start cycle. Circuit operation will not start until the supply voltage (VBT+) goes
above 3.95V dc.
2-10. -22 Volts
The raw voltage needed to run the LCD bias is provided by the TLC555 timer (U19), and
transformer T2. These two components work as a boost circuit to change the battery
voltage to ≈24V dc. Q4, in addition to working in the boost circuit, inverts the 24V dc
through CR8, C52, and C68. VR1 controls this voltage to ≈-22V dc. This is necessary
because there is no feedback to U19. A feed forward path, R61, helps control the supply
voltage as the battery voltage changes. The duty cycle changes, which causes the
frequency of the boost circuit to change from 88 to 140 kHz as the battery voltage
changes from 4V to 6V dc. The LCD supply is controlled by the microcontroller through
signal LCD_PWR, which when high, turns U19 on.

2-11. VEE

The VEE supply controls the contrast of the LCD. U8 is an EEPOT that is controlled by
the microcontroller. The voltage appearing at the wiper pin is buffered by an op amp
(part of U25). The other half of U25 is used as a difference amplifier to sum the wiper
signal with a voltage, which is temperature sensitive. The temperature-sensitive voltage
comes from Q18, which is biased as a diode and has a temperature sensitivity of ≈2.2
mV/degree. The default for contrast is ≈-16.6V dc, with a range of -15V dc (minimum
contrast) to -18.5V dc (Maximum contrast).

2-12. VDD

The +5V dc supply is generated by first doubling the VCC supply. U29, CR4, C69, and
C67 form the voltage doubler circuit. Capacitor C69 is charged to VCC minus one diode
drop, when the CAP+ terminal of U29 goes to ground. When the CAP+ terminal goes to
VCC, the sum of the voltage across C69 and VCC is applied to C67 through the second
diode in CR4. U31 is a low dropout 5V regulator.

2-13. VSS

The negative analog supply (VSS) is generated by U23 and Q12. U23 works by charging
C65 to ≈ 6.6V dc, from pin 8 of U23, and then inverts C65 and places it in parallel with
C64. Q12 assures that VDD is up before VSS is applied to the analog circuitry.

2-14. VREF

The reference voltage for the two a/d converters is generated by U28, Z5 and U24. U28
provides 2.5V dc ±0.4%. which is divided into 2.1154V dc by Z4. U24 buffers the
reference voltage (2.1154V dc) for use by the a/d converters and their input dividers.
Theory of Operation
Circuit Descriptions
2
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