JUKI 6100 Technical Manual page 66

J22
A-
B-
C-
D-
A-
B-
C
-
D
-
J22
READY(N)
6
CHECK
7
SEL1
(N)
9
SEL2(N)
10
5
-|^>o
M
V
5
V
-+5V
C1-Lg
1
C
2
T
1
!
±0A[i/50V
74LS153
1C0
1C1
1Y
1C2
2Y
1C3
2C0
2C1
2C2
2C3
B
A
BIT
2
BIT
1
BITO
COVER
OPEN
To
MCU1
J05
From
MCU1
J05
A
B
C
D
SEL1
(N) 0 0
1 1
SEL2
(N) 0
1
0
1
Fig.
7.25
Operation panel
circuit (partial)
-
63
-