JUKI 6100 Technical Manual page 58

Strobe
Busy
P
A
R
A
L
L
E
L
Op-panel
Switch
Inputs
Serial
I/O
Switch
Inputs
Serial
I/O present
Timer
In
Timer Out
PC2
PC1
PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PBO
PB1
PB2
PB3
PB4
PB5
PB6
TIMIN
TIMOUT
8
1
5
5
P
I
A
PCO
PC3
PC4
PC5
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
M/IO
ALE
RD
WR
Interrupt to
MPU
Ready lamp
Check lamp
Audible alarm
Multiplexed
Address/Data
Memory/IO
Address Latch
Read
Write
Fig.
7.11
The
microprocessor of
the
MCU-1
board
runs
under
control of
a
program which
is
contained
in
Read Only
Memory
(ROM). Depending on
the
type of microproces-
sor
(8031
or
8051)
this
control
program
may
be divided
between two
devices
(8051 and
separate
ROM)
or
it
may
be
resident in
only
one
ROM.
Further, the
program
may
be contained
in either a
Masked
(M-ROM)
or
Eraseable/Programma-
ble
ROM
(EP-ROM). The
following
is
a
list
of the possible
combinations
of micro-
processors
and
associated
ROMs.
805
1
MPU
(4K
M-ROM)
+ 2332 (4K
M-ROM)
=
TOTAL
8K
805
1
MPU
(4K
M-ROM)
+ 2732 (4K
EP-ROM) =
TOTAL
8K
803
1
MPU
+ 2764 (8K
EP-ROM) =
TOTAL
8K
The 8031/8051 microprocessor
serves as
the
main
control
element of
the
6100,
it
operates
at a
fundamental clock frequency of 7.37
MHZ.
Fig.
7.12
shows
the base
timing relationships for a
ROM
fetch cycle.
The
low
byte of the
ROM
address
is
presented
on
the
multiplexed address/data
lines.
The
negative transition of the
ALE
line
causes the
low
address
byte
to
be latched into
a
74LS373.
The
high
address
bits
(A8
~
A
12) are
present
on
port
B
bits
0 through 4
respectively
and
stay active for
the
entire
read
cycle.
Once
the
low
address
byte has been
latched
the
address/data
lines are
placed
in a
high
impedance
state
and data presented
from
the
ROM
is
read into the
MPU
during
the positive transition
of the
PSEN
signal line.
The
PSEN
line
is
used
strictly
for the
purpose of reading
from
a
con-
trol
ROM.
ALE
j
\
/ V
a
/
\
r
PSEN
'
AD0-AD7 Data
X
Address X
Data
X Address X
Data X
AD8-AD12
X~
Address X Address
X
Fig.
7.12
ROM
read timing diagram
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55
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