JUKI 6100 Technical Manual page 59

The
instructions
which
are
fetched
from
the control
ROM
are
decoded and
pro-
cessed
by
the
8031/8051.
Instructions
which
require reading
from
or writing
to
RAM
make
use of separate
Read
and Write control
lines. Fig.
7.13
illustrates
the
timing of
a
write
operation
to
RAM.
Once
again the
low order byte of the address
is
presented
on
the multiplexed address/data
lines
and
is
latched
by
the negative
transition
of the
ALE
line.
At
the
same
time
that
the
low
order address byte
is
being latched address
lines
All
through
A13
of the high address byte
are
decoded
to
provide chip enable
(CE)
lines to the
RAM
chips.
The
chip enable
lines
are
active for
each of the
2K
increments
of available
RAM
up
to
a
maximum
of 8K.
With
the address latched
and decoded
the
MPU
will
now
place the write data
on
the address/data
lines.
The
data
will
be placed
in
RAM
during the
positive
transi-
tion
of the Write control
line.
During
the write cycle the
PSEN
line will
remain
inactive
which
disables
the control
ROM
from
decoding the address
and attempting
to
present
any
output data to the address/data
bus.
ALE
/
\
/
PSEN
WR
\
-J
AD0-AD7
Instr
X
Address
X
Data
X
Address
AD8-AD13
X
Address
X
CE
/
Fig.
7.13
RAM
write
timing diagram
Fig.
7.14
is
the
timing diagram
for a
RAM
read
cycle.
As
with
the write
operation
the
ALE, PSEN,
Address/data
lines
and
CE
line
timings
are identical.
The
main
difference
in
the
read timing sequence
is
the
amount
of time
that the actual read
data
is
at
a valid
level.
The
time
during
which
data
is
valid
is
a
function of the
RAM
access
time
and
should not exceed
400
nanoseconds.
Data from
RAM
is
latched
in
the
MPU
at
the positive transition of the
Read
Data
(RD)
line.
ALE
PSEN
RD
J
\
r
a r
AD0-AD7
Instr
X~
Address
)
(
Data
)
—
(
Address
AD8-AD13 )T~
Address
X
CE
a r
Fig.
7.14
RAM
read timing
diagram