Figure 5-11. Level-Ack Mode Output Timing - National Instruments DIO 6533 User Manual

High-speed digital i/o boards for pci, pxi, compactpci, at, eisa, or pcmcia bus systems
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REQ
ACK
Output Data
(REQ-edge latching)
Output Data
(REQ-edge
latching disabled)
Parameter
Input Parameters
t
REQ pulse width
rr*
t
REQ inactive duration
r*r
t
ACK to next REQ
ar
Output Parameters
t
ACK pulse width
aa*
t
REQ to ACK inactive
ra*
REQ inactive to new output data
t
r*do
(with REQ-edge latching)
t
REQ to new output data
rdo
(with REQ-edge latching disabled)
t
Output data valid to ACK
doa
(with REQ-edge latching disabled)
1
t
(min) = 25 + programmable delay
doa
© National Instruments Corporation
t ar
t r*r
t aa*
t ra*
t doa
Description
All timing values are in nanoseconds.

Figure 5-11. Level-ACK Mode Output Timing

5-13
Chapter 5
t rr*
t r*do
t rdo
Minimum
75
75
0
225
100
0
0
1
25
DIO 6533 User Manual
Signal Timing
Maximum
200
50

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