Figure 5-22. Trailing-Edge Mode Input Timing - National Instruments DIO 6533 User Manual

High-speed digital i/o boards for pci, pxi, compactpci, at, eisa, or pcmcia bus systems
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Chapter 5
Signal Timing
REQ
ACK
Input Data
(REQ-edge latching)
Input Data
(REQ-edge
latching disabled)
Parameter
Input Parameters
t
REQ pulse width
rr*
t
REQ inactive duration
r*r
t
Input data setup to REQ inactive
dir*
(with REQ-edge latching)
t
Input data hold from REQ inactive
r*di
(with REQ-edge latching)
Input data setup to REQ
t
dir
(with REQ-edge latching disabled)
Input data hold from ACK
t
adi
(with REQ-edge latching disabled)
Output Parameters
t
ACK pulse width
aa*
t
ACK inactive to next REQ inactive
a*r*
1
t
(min) = 225 + programmable delay
aa*
2
t
(max) = 275 + programmable delay
aa*
DIO 6533 User Manual
t r*r
t aa*
t r*di
t dir*
t adi
t dir
Description
All timing values are in nanoseconds.

Figure 5-22. Trailing-Edge Mode Input Timing

5-26
t rr*
t a*r*
Minimum
75
75
0
10
0
0
1
225
0
© National Instruments Corporation
t adi
Maximum
2
275

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