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National Instruments DIO 6533 User Manual

High-speed digital i/o boards for pci, pxi, compactpci, at, eisa, or pcmcia bus systems
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DIO 6533

User Manual

High-Speed Digital I/O Boards for
PCI, PXI, CompactPCI, AT, EISA, or
PCMCIA Bus Systems
July 1997 Edition
Part Number 321464B-01
© Copyright 1997 National Instruments Corporation. All rights reserved.

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Summary of Contents for National Instruments DIO 6533

  • Page 1: User Manual

    DIO 6533 User Manual High-Speed Digital I/O Boards for PCI, PXI, CompactPCI, AT, EISA, or PCMCIA Bus Systems July 1997 Edition Part Number 321464B-01 © Copyright 1997 National Instruments Corporation. All rights reserved.
  • Page 2 Korea 02 596 7456, Mexico 5 520 2635, Netherlands 0348 433466, Norway 32 84 84 00, Singapore 2265886, Spain 91 640 0085, Sweden 08 730 49 70, Switzerland 056 200 51 51, Taiwan 02 377 1200, United Kingdom 01635 523545 National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin, TX 78730-5039 Tel: (512) 794-0100...

  • Page 3: Important Information

    National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.

  • Page 4: Table Of Contents

    Related Documentation... xiii Customer Communication ... xiv Chapter 1 Introduction About the DIO 6533 Devices... 1-1 Using PXI with CompactPCI... 1-2 What You Need to Get Started ... 1-3 Software Programming Choices ... 1-4 National Instruments Application Software ... 1-4 NI-DAQ Driver Software ...
  • Page 5 Board and RTSI Clocks ... 4-8 RTSI Triggers ... 4-8 Data Signal Connections ... 4-9 Unstrobed I/O... 4-10 Strobed I/O... 4-12 DIO 6533 User Manual Base I/O Address Selection... 2-6 DMA Channel Selection ... 2-6 Interrupt Channel Selection... 2-6 © National Instruments Corporation...
  • Page 6 Output ... 5-10 Level-ACK Mode Timing Specifications... 5-11 Input... 5-14 Output ... 5-14 Leading-Edge Mode Timing Specifications... 5-16 Long-Pulse Mode Timing Specifications ... 5-20 Input... 5-23 Output ... 5-23 Trailing-Edge Mode Timing Specifications ... 5-25 Table of Contents DIO 6533 User Manual...
  • Page 7 8255 Emulation Mode Output ... 5-7 Figure 5-7. 8255 Emulation Timing... 5-8 Figure 5-8. Level-ACK Mode Input ... 5-10 Figure 5-9. Level-ACK Mode Output... 5-11 Figure 5-10. Level-ACK Mode Input Timing... 5-12 DIO 6533 User Manual viii © National Instruments Corporation...
  • Page 8 PC AT 16-Bit DMA Channel Assignment Map ... 2-9 Table 3-1. 6533 Handshaking Protocols ... 3-11 Table 4-1. Signal Descriptions ... 4-3 Table 4-2. Control Signal Summary ... 4-7 © National Instruments Corporation Table of Contents DIO 6533 User Manual...

  • Page 9: About This Manual

    DIO 6533 (formerly called DIO-32HS) family of devices, and contains information concerning their operation and programming. Unless otherwise noted, text applies to all devices in the DIO 6533 family. The devices named DIO-32HS and 6533 are the same in functionality; their primary difference is the bus interface.

  • Page 10: Conventions Used In This Manual

    National Instruments Documentation The DIO 6533 User Manual is one piece of the documentation set for your DAQ system. You could have any of several types of documents, depending on the hardware and software in your system. Use the...

  • Page 11: Related Documentation

    DAQ hardware, and application hints. Software documentation—You may have both application software and NI-DAQ software documentation. National Instruments application software includes LabVIEW, LabWindows ComponentWorks, and VirtualBench. After you set up your hardware system, use either your application software documentation or the NI-DAQ documentation to help you write your application.

  • Page 12: Customer Communication

    About This Manual Customer Communication National Instruments wants to receive your comments on our products and manuals. We are interested in the applications you develop with our products, and we want to help if you have problems with them. To make it easy for you to contact us, this manual contains comment and configuration forms for you to complete.

  • Page 13: Introduction

    About the DIO 6533 Devices Thank you for buying a National Instruments DIO 6533 device. The 6533 devices are 32-bit, parallel digital I/O interfaces for PC-compatible computers, or PXI or CompactPCI chassis. The 6533 devices offer digital data acquisition, digital waveform generation, and high-speed, flexible handshaking.

  • Page 14: Using Pxi With Compactpci

    Chapter 1 Introduction Each 6533 device contains the National Instruments DAQ-DIO chip, providing two independent channels of digital input and output, pattern generation, and handshaking. Each channel offers the following functions: • • • • • • • With 6533 devices, you can use your computer or chassis as a digital I/O tester, logic analyzer, or system controller for laboratory testing, production testing, and industrial process monitoring and control.

  • Page 15: What You Need To Get Started

    Damage may result if these lines are driven by the sub-bus. What You Need to Get Started To set up and use your DIO 6533 device, you will need the following: © National Instruments Corporation Table 1-1. Pins Used by the PXI-6533 Device...

  • Page 16: Software Programming Choices

    The LabVIEW Data Acquisition VI Library, a series of VIs for using LabVIEW with National Instruments DAQ hardware, is included with LabVIEW. The LabVIEW Data Acquisition VI Library is functionally equivalent to the NI-DAQ software.

  • Page 17: Ni-Daq Driver Software

    An example of a low-level function is writing directly to registers on the DAQ device. NI-DAQ does not sacrifice performance of National Instruments DAQ devices because it lets multiple devices operate at their peak performance, even simultaneously.

  • Page 18: Register-Level Programming

    AT-DIO-32HS requires version 5.0 or later. The PXI-6533 or DAQCard-6533 requires version 5.1 or later. Register-Level Programming The final option for programming any National Instruments DAQ hardware is to write register-level software. Writing register-level programming software can be very time-consuming and inefficient and is not recommended for most users.

  • Page 19: Optional Equipment

    • • • Some cables and accessories require use of the 68 to 50-pin DIO 6533 device adaptor, detailed in Appendix B, For more specific information about these products, refer to your National Instruments catalogue or web site, or call the office nearest you.

  • Page 20: Unpacking

    • • • • • DIO 6533 User Manual Ground yourself via a grounding strap or by holding a grounded object. Touch the antistatic package to a metal part of your computer chassis before removing the device from the package.

  • Page 21: Installation And Configuration

    Installation and Configuration This chapter explains how to install and configure your DIO 6533 device. Software Installation Install your software before you install your 6533 device. Refer to the appropriate release notes indicated below for specific instructions on the software installation sequence.

  • Page 22: Installing The Pxi-6533

    5. Insert the PXI-6533 in the selected 5 V slot. Use the injector/ejector 6. Screw the front panel of the PXI-6533 to the front panel mounting DIO 6533 User Manual electricity that might be on your clothes or body. do not force the device into place.

  • Page 23: Installing The At-Dio-32Hs

    DAQCard-6533. When plugging and unplugging the cable, always grasp the cable by the connector. Never pull directly on the I/O cable to unplug it from the DAQCard-6533. Chapter 2 Installation and Configuration for the completed installation. DIO 6533 User Manual...

  • Page 24: Pci, Pxi, And Daqcard Device Configuration

    The PCI-DIO-32HS, PXI-6533, and DAQCard-6533 are completely software configurable. The system software automatically allocates all device resources, including base memory address and interrupt level. These devices do not require DMA controller resources from your computer. DIO 6533 User Manual Portable Computer PCMCIA Socket I/O Cable Figure 2-1.

  • Page 25: At Device Configuration

    DAQ device. A non-Plug and Play system is a system in which the Configuration Manager has not been installed and which does not contain any non-National Instruments Plug and Play products. Use a configuration utility, such as the NI-PnP or Intel configuration utilities, to enter the base address, DMA, and interrupt selections, and the application software assigns them to the device.

  • Page 26: Base I/O Address Selection

    Tables 2-1, 2-2, and 2-3 provide information concerning possible conflicts in base address, DMA channel, and interrupt channel assignment when configuring your AT-DIO-32HS device. DIO 6533 User Manual Table 2-1. PC AT I/O Address Map I/O Address Range (Hex) 100 to 1EF —...
  • Page 27 Bisynchronous (BSC) Communications (alternate) 390 to 393 Cluster Adapter 0 394 to 39F — 3A0 to 3A9 BSC Communications (primary) 3AA to 3AF — 3B0 to 3BF Monochrome Display/Parallel Printer Adapter 0 Chapter 2 Installation and Configuration Device DIO 6533 User Manual...

  • Page 28: Table 2-2. Pc At Interrupt Assignment Map

    Chapter 2 Installation and Configuration Table 2-2 shows the PC AT interrupt assignments. DIO 6533 User Manual Table 2-1. PC AT I/O Address Map (Continued) I/O Address Range (Hex) 3C0 to 3CF Enhanced Graphics Adapter, VGA 3D0 to 3DF Color/Graphics Monitor Adapter, VGA 3E0 to 3EF —...

  • Page 29: Table 2-3. Pc At 16-Bit Dma Channel Assignment Map

    Timer Channel 0 Output Table 2-3. PC AT 16-Bit DMA Channel Assignment Map Channel AT-MIO-16 Series – default AT-MIO-16 Series – default AT-DIO-32F – default AT-DIO-32F – default Cascade for DMA Controller #1 (channels<0..3>) Installation and Configuration Device Device DIO 6533 User Manual...

  • Page 30: Hardware Overview

    This chapter provides an overview of the hardware functions of your DIO 6533 device. Each 6533 device contains the National Instruments DAQ-DIO chip, a 32-bit general-purpose digital I/O interface. The DAQ-DIO chip enables the 6533 device to perform single-line and single-point input and output, digital data acquisition, digital waveform generation, and high-speed data transfer using a wide range of handshaking protocols.

  • Page 31: Figure 3-1. Pci-Dio-32Hs/Pxi-6533 Block Diagram

    Chapter 3 Hardware Overview Data Lines (32) MITE PCI Interface EEPROM DIO 6533 User Manual Data Latches Internal Interface FIFOs DMA/ Handshaking Interrupt DAQ-DIO Requests Counters Clock Selection Timers 20 MHz RTSI Oscillator Interface RTSI/PXI Trigger Bus Figure 3-1. PCI-DIO-32HS/PXI-6533 Block Diagram...

  • Page 32: Figure 3-2. At-Dio-32Hs Block Diagram

    FIFOs Drivers DMA/ Handshaking Interrupt DAQ-DIO Requests Control Counters Request Clock Processing Selection Timers 20 MHz RTSI Oscillator Interface RTSI Bus Figure 3-2. AT-DIO-32HS Block Diagram Chapter 3 Hardware Overview Data Lines (32) Control Lines (8) DIO 6533 User Manual...

  • Page 33: Unstrobed I/O

    Therefore, you can use the REQ and STOPTRIG lines as extra data inputs, and the ACK and PCLK lines as extra data outputs. DIO 6533 User Manual Data Latches Internal...

  • Page 34: Strobed I/O-Pattern Generation And Handshaking

    You can select either a rising edge or a falling edge as a trigger signal. You can also trigger when the 6533 device detects a specified digital pattern on its data lines. © National Instruments Corporation Chapter 3 Hardware Overview DIO 6533 User Manual...

  • Page 35: Pattern And Change Detection

    • • • DIO 6533 User Manual Generate a start trigger to begin a digital data acquisition operation Generate a stop trigger to end a digital data acquisition operation A mask, declaring which data bits you wish to examine...

  • Page 36: Change Detection

    Compare acquired data to the pattern, after a request pulse strobes the data in (typically used for stop triggers). Request Timing section in Chapter 5, Chapter 3 Hardware Overview Postive: Search for Match Signal Timing, for the timing DIO 6533 User Manual...

  • Page 37: Message Generation

    ACK signals that the 6533 device sends to the peripheral device and of the REQ signals DIO 6533 User Manual Transfer Rates Generate a message upon acquisition of a specified input pattern Generate a message every time the 6533 device transfers a data point.

  • Page 38: 8255 Emulation

    The 8255 emulation protocol emulates the strobed protocols obeyed by the 8255 and 82C55 PPI chips—chips that are used, for example, on the National Instruments PC-DIO-24 and PC-DIO-96/PnP. Because of faster response times, a wider data path, and FIFO buffering, 8255 emulation mode offers much higher data transfer rates than an actual 8255 chip.

  • Page 39: Burst Mode

    8255 emulation mode can communicate with a 6533 device in long pulse mode, if you select ACK and REQ to be active low. DIO 6533 User Manual shows similarities and differences among the 6533 device shows peak handshaking rates for typical cable lengths. The...

  • Page 40: Table 3-1. 6533 Handshaking Protocols

    Before ACK Leading-Edge and between Pulse transfers For pulse width Long Pulse, and between 8255 transfers Emula-tion, PC-DIO-24, PC-DIO-96/PnP, 8255, 82C55 For pulse width Trailing-Edge and between Pulse transfers For clock speed Burst DIO 6533 User Manual...

  • Page 41: Starting A Handshaking Transfer

    6533 device at the same time, when you start the actual data transfer. For buffered operations, therefore, use the second startup method, controlling the line polarities. DIO 6533 User Manual Control the configuration and startup sequence. Select compatible line polarities and default line levels.

  • Page 42: Controlling Line Polarities

    Burst mode is the fastest handshaking protocol, especially for short cables. Your system bus should be as free as possible from unrelated activity. Minimize the number of other I/O cards active in the system. 3-13 Chapter 3 Hardware Overview Table 3-1, which can be lowered DIO 6533 User Manual...
  • Page 43 Chapter 3 Hardware Overview • • DIO 6533 User Manual Direct-memory access (DMA) transfers are faster than interrupt-driven transfers, especially for pattern generation. By default, the software uses DMA if available. The PCI-DIO-32HS always supports DMA transfers. The PXI-6533 supports DMA if inserted into a peripheral slot that allows bus arbitration (bus mastering).

  • Page 44: Signal Connections

    Signal Connections This chapter describes how to make input and output signal connections to your DIO 6533 device via the device I/O connector and RTSI connector. The I/O connector for the 6533 device has 68 pins. You can connect the 6533 device to 68-pin accessories through an SH68-68-D1 shielded cable or an R6868 ribbon cable.

  • Page 45: Figure 4-1. 6533 Device I/O Connector Pin Assignments

    REQ2 pins, with software. This can be useful when performing two-way ACK/REQ handshaking between two 6533 devices over an SH68-68-D1 or similar cable, because it allows you to connect one device’s ACK pin to the DIO 6533 User Manual 34 68 DIOD7...

  • Page 46: Signal Descriptions

    When not configuring the 6533 device for group operations, you can use the ACK<1..2> lines as extra, general-purpose output lines (OUT<3..4>). Chapter 4 Signal Connections Description DIO 6533 User Manual...
  • Page 47 28, 57–58, 60–61 29, 31–32, DIOD<0..7> 34, 63–64, 66–67 DIO 6533 User Manual Table 4-1. Signal Descriptions (Continued) Signal Type Control Group 1 and group 2 stop triggers—You can use rising or falling edges on these lines to end pattern generation operations.
  • Page 48 With an R6868 ribbon cable, you can use these lines as additional ground references. With an SH68-68-D1, however, these signals are not connected. Chapter 4 Signal Connections Description DIO 6533 User Manual...

  • Page 49: Signal Characteristics

    • • • • DIO 6533 User Manual Drive current—After being enabled, all lines that can be configured for output sink at least 24 mA at 0.4 V, and source at least 24 mA at 2.4 V. DAQCard-6533—Your PCMCIA socket may not provide sufficient power to drive all outputs at 24 mA.

  • Page 50: Control Signal Summary

    RTSI bus interface. The PCI-DIO-32HS and AT-DIO-32HS each contains a RTSI connector and an interface to the National Instruments RTSI bus. The RTSI bus provides seven trigger lines and a system clock line. All National Instruments AT and PCI boards that have RTSI bus connectors can be cabled together inside a computer to share these signals.

  • Page 51: Board And Rtsi Clocks

    Any 6533 device control signal can connect to a RTSI or trigger bus line. You can drive output control signals onto the bus and receive input control signals from the bus. scheme. DIO 6533 User Manual Figure 4-2 shows the signal connection © National Instruments Corporation...

  • Page 52: Data Signal Connections

    Ports DIOA, DIOB, DIOC, and DIOD are port numbers 0, 1, 2, and 3, respectively. © National Instruments Corporation Chapter 4 Trigger 20 MHz Timebase Figure 4-2. RTSI Bus Signal Connection Signal Connections DAQ-DIO REQ<1..2> ACK<1..2> (STARTTRIG<1..2>) STOPTRIG<1..2> PCLK<1..2> Switch DIO 6533 User Manual...

  • Page 53: Unstrobed I/O

    DIOB<0..3> configured for wired-OR output. Unstrobed input applications include sensing external device states, such as the state of the switch shown in the figure, and receiving low-speed TTL signals. Unstrobed output applications include driving external controls and indicators such as the LED shown in low-speed TTL signals.

  • Page 54: Figure 4-3. Example Of Data Signal Connections

    +5 V TTL Signal +5 V Switch Open-Collector +5 V Switch I/O Connector © National Instruments Corporation +5 V DPULL 6533 Device Figure 4-3. Example of Data Signal Connections 4-11 Chapter 4 Signal Connections DIOA<4..7> DIOA<0..3> DIOB<0..3> DIO 6533 User Manual...

  • Page 55: Strobed I/O

    • • DIO 6533 User Manual It does not rely on pull-up resistors. It is independent of the state of the DPULL line. It has high current drive for both its logic high and logic low states.

  • Page 56: Timing Connections

    6533 device or reset its drivers. © National Instruments Corporation Signal Timing, details the connection and timing of each 4-13 Chapter 4 Signal Connections resistors. If you drive DIO 6533 User Manual...

  • Page 57: Power Connections

    Make sure your 6533 device and your peripheral device share a common ground reference. Connect one or more 6533 device GND lines to the ground reference of your peripheral device. DIO 6533 User Manual • Power rating: +4.65 to +5.25 VDC at 1 A •...
  • Page 58 Route signals to the device carefully. Keep cabling away from noise sources. The most common noise source in a PC-based system is the video monitor. As much as possible, separate the monitor from any unshielded signal wiring. 4-15 Chapter 4 Signal Connections Figure 4-4 shows DIO 6533 User Manual...

  • Page 59: Figure 4-4. Transmission Line Terminations

    The following additional recommendations apply for all signal connections to your 6533 device: • • • DIO 6533 User Manual 6533 Device +5 V +5 V Figure 4-4. Transmission Line Terminations Separate 6533 device signal lines from high-current or high-voltage lines.

  • Page 60: Signal Timing

    Signal Timing This chapter provides detailed timing specifications for DIO 6533 pattern generation and for the various full, two-way handshaking modes. Pattern-Generation Timing Pattern-generation timing is similar for digital data acquisition (input) and digital waveform generation (output). Data transfers are timed by request pulses, carried on the REQ pin.

  • Page 61: Request Timing

    Figure 5-3 low and return high. The request pulse low and high durations must be at least 20 ns each. The minimum period is 50 ns. DIO 6533 User Manual Programmable = Interval x Timebase t lw Programmable = One Timebase...

  • Page 62: Trigger Timing

    10 ns 20 ns Description Cycle time Width of low pulse Width of high pulse Propagation time to valid output data Setup time Hold time Figure 5-3. External Request Timing Chapter 5 Signal Timing DIO 6533 User Manual...

  • Page 63: Handshake Timing

    The 8255 emulation mode handshakes in a manner compatible with an 8255 or 82C55 Programmable Peripheral Interface (PPI). The 8255 and 82C55 PPIs are digital I/O chips used on many digital DAQ devices, such as the National Instruments PC-DIO-24 and PC-DIO-96/PnP. DIO 6533 User Manual is pulse width.

  • Page 64: Input

    6533 device REQ line carries the 8255 STB input signal, and the 6533 device ACK line carries the 8255 IBF output signal. Both lines are active low. © National Instruments Corporation Chapter 5 Signal Timing DIO 6533 User Manual...

  • Page 65: Output

    6533 device terminology differs from 8255 terminology. In output mode, the 6533 device REQ line carries the 8255 ACK input signal, and the 6533 device ACK line carries the 8255 OBF output signal. Both lines are active low. DIO 6533 User Manual Programmable Delay Send Wait Figure 5-5.

  • Page 66: Figure 5-6. 8255 Emulation Mode Output

    Asserted © National Instruments Corporation Initial State ACK Cleared Programmable Delay Output Data, Then Send ACK Wait Figure 5-6. 8255 Emulation Mode Output Chapter 5 Signal Timing Wait Data When 6533 Device Has Data to Output DIO 6533 User Manual...

  • Page 67: 8255 Emulation Mode Timing Specifications

    REQ falling edge to ACK rising edge Output data valid to ACK falling edge doa* REQ rising edge to output data invalid All timing values are in nanoseconds. DIO 6533 User Manual t r*r t a*r t r*a t aa*...

  • Page 68: Other Asynchronous Modes

    6533 device latches data out of the I/O connector on the REQ edge. Which edge of REQ is used (rising or falling) depends on the handshaking mode and the REQ polarity. Chapter 5 Signal Timing DIO 6533 User Manual...

  • Page 69: Output

    When REQ Asserted Wait Clear ACK When REQ Unasserted * With REQ-edge latching enabled, the data read is from the last active-going REQ edge. DIO 6533 User Manual Programmable Delay Programmable Delay Send Wait Figure 5-8. Level-ACK Mode Input 5-10...

  • Page 70: Level-Ack Mode Timing Specifications

    ACK Cleared Programmable Delay Programmable Delay Send Wait Figure 5-9. Level-ACK Mode Output 5-11 show the timing diagrams for level-ACK mode. 5-11 Chapter 5 Signal Timing Wait Data When 6533 Device Has Data to Output, Output Data* DIO 6533 User Manual...

  • Page 71: Figure 5-10. Level-Ack Mode Input Timing

    Input data hold from ACK (with REQ-edge latching disabled) Output Parameters ACK pulse width REQ to ACK inactive All timing values are in nanoseconds. DIO 6533 User Manual t ar t r*r t rr* t aa* t ra* t dir(1)

  • Page 72: Figure 5-11. Level-Ack Mode Output Timing

    Description All timing values are in nanoseconds. Figure 5-11. Level-ACK Mode Output Timing 5-13 Chapter 5 Signal Timing t r*do t rdo Minimum Maximum — — — — — — DIO 6533 User Manual...

  • Page 73: Leading-Edge Mode

    To slow down the handshake, you can specify a data-settling delay to occur before the ACK signal. This delay increases the setup time from valid output data to the ACK signal. DIO 6533 User Manual 5-14 © National Instruments Corporation...

  • Page 74: Figure 5-12. Leading-Edge Mode Input

    REQ edge. © National Instruments Corporation Programmable Delay Programmable Clear Send Pulse Pulse Wait Figure 5-12. Leading-Edge Mode Input 5-15 Chapter 5 Signal Timing Wait Space When 6533 Device Has Space For Data, Input Data* Delay DIO 6533 User Manual...

  • Page 75: Leading-Edge Mode Timing Specifications

    Pulse When REQ Unasserted * With REQ-edge latching enabled, the data written is delayed until the next inactive-going REQ edge. Leading-Edge Mode Timing Specifications Figures 5-14 mode. DIO 6533 User Manual Initial State ACK Cleared Programmable Delay Programmable Delay Send...

  • Page 76: Figure 5-14. Leading-Edge Mode Input Timing

    Description Figure 5-14. Leading-Edge Mode Input Timing 5-17 Chapter 5 Signal Timing t adi Minimum Maximum — — — — — — — — — DIO 6533 User Manual...

  • Page 77: Figure 5-15. Leading-Edge Mode Output Timing

    (with REQ-edge latching) REQ to new output data (with REQ-edge latching disabled) Output data valid to ACK (with REQ-edge latching disabled) (min) = 25 + programmable delay DIO 6533 User Manual t r*a* t ar t r*r t rr* t aa*...

  • Page 78: Long-Pulse Mode

    Figures 5-16 Programmable Delay Send ACK Pulse Programmable Delay Wait Figure 5-16. Long-Pulse Mode Input 5-19 Chapter 5 Signal Timing 5-17 show long-pulse mode input Wait Space When 6533 Device Has Space For Data, Input Data* DIO 6533 User Manual...

  • Page 79: Long-Pulse Mode Timing Specifications

    Pulse When REQ Unasserted * With REQ-edge latching enabled, the data written is delayed until the next inactive-going REQ edge. Long-Pulse Mode Timing Specifications Figures 5-18 DIO 6533 User Manual Initial State ACK Cleared Programmable Delay Send ACK Pulse Programmable...

  • Page 80: Figure 5-18. Long-Pulse Mode Input Timing

    Description All timing values are in nanoseconds. Figure 5-18. Long-Pulse Mode Input Timing 5-21 Chapter 5 Signal Timing t adi Minimum Maximum — — — — — — — — — DIO 6533 User Manual...

  • Page 81: Figure 5-19. Long-Pulse Mode Output Timing

    (with REQ-edge latching) REQ to new output data (with REQ-edge latching disabled) Output data valid to ACK (with REQ-edge latching disabled) (min) = 125 + programmable delay DIO 6533 User Manual t ar t r*r t rr* t aa* t doa Description All timing values are in nanoseconds.

  • Page 82: Trailing-Edge Mode

    To slow down the handshake, you can specify a data-settling delay to increase the ACK pulse width and, therefore, the setup time from valid output data to the trailing edge of the ACK signal. © National Instruments Corporation 5-23 DIO 6533 User Manual...

  • Page 83: Figure 5-20. Trailing-Edge Mode Input

    Unasserted Wait When REQ Asserted Initial State ACK Cleared * With REQ-edge latching enabled, the data read is from the last inactive-going REQ edge. DIO 6533 User Manual Programmable Delay Send Programmable Delay Clear Wait Figure 5-20. Trailing-Edge Mode Input...

  • Page 84: Trailing-Edge Mode Timing Specifications

    ACK Cleared Programmable Delay Send Programmable Delay Clear Wait Figure 5-21. Trailing-Edge Mode Output 5-23 show the timing diagrams for trailing-edge 5-25 Chapter 5 Signal Timing Wait Data When 6533 Device Has Data to Output, Output Data* DIO 6533 User Manual...

  • Page 85: Figure 5-22. Trailing-Edge Mode Input Timing

    Output Parameters ACK pulse width ACK inactive to next REQ inactive a*r* (min) = 225 + programmable delay (max) = 275 + programmable delay DIO 6533 User Manual t r*r t aa* t r*di t dir* t adi t dir Description All timing values are in nanoseconds.

  • Page 86: Burst Mode

    Description All timing values are in nanoseconds. Figure 5-23. Trailing-Edge Mode Output Timing 5-27 Chapter 5 Signal Timing t a*r* t r*do(1) t r*do(2) Minimum Maximum — — — — — DIO 6533 User Manual...

  • Page 87: Burst Mode Timing Specifications

    D2 is data point number 2, and so on. Figures 5-26 PCLK Data In DIO 6533 User Manual shows a burst mode transfer data input example, and shows a burst mode transfer data output example, where D1 through 5-29 show the burst mode timing diagrams.

  • Page 88: Figure 5-25. Output Burst Mode Transfer Example

    Chapter 5 Signal Timing PCLK Data Out Figure 5-25. Output Burst Mode Transfer Example © National Instruments Corporation 5-29 DIO 6533 User Manual...

  • Page 89: Figure 5-26. Burst Mode Output Timing (Default)

    PCLK to ACK valid Hold time from PCLK to ACK invalid PCLK to output data valid Hold time from PCLK to output data invalid All timing values are in nanoseconds. DIO 6533 User Manual t pc t pl t rs Description Figure 5-26.

  • Page 90: Figure 5-27. Burst Mode Input Timing (Default)

    Description Figure 5-27. Burst Mode Input Timing (Default) 5-31 Chapter 5 Signal Timing t ah t rh t dih Minimum Maximum — — — — /2 – 5 /2 + 5 — — DIO 6533 User Manual...

  • Page 91: Figure 5-28. Burst Mode Output Timing (Pclk Reversed)

    = programmable delay from 100 to 700 ns, or 50 ns if programmable delay is 0. Timebase stability for the board 20 MHz clock source is 50 ppm. All timing values are in nanoseconds. DIO 6533 User Manual t pc t rs Description Figure 5-28.

  • Page 92: Figure 5-29. Burst Mode Input Timing (Pclk Reversed)

    Description Figure 5-29. Burst Mode Input Timing (PCLK Reversed) 5-33 Chapter 5 Signal Timing t ah t rh t dih Minimum Maximum — — — — — — — DIO 6533 User Manual...
  • Page 93 Specifications This appendix lists the specifications for the DIO 6533 devices. These specifications are typical at 25 C unless otherwise noted. PCI-DIO-32HS, PXI-6533, AT-DIO-32HS, and DAQCard-6533 Devices Digital I/O Number of channels ...32 input/output; Compatibility ...TTL/CMOS (standard or Hysteresis ...500 mV 1.
  • Page 94 Input low current for control lines Input high current for control lines Input low current for CPULL/DPULL Input high current for CPULL/DPULL DIO 6533 User Manual Level = 0.4 V) DPULL high — DPULL low — = 2.4 V) DPULL high —...

  • Page 95: Pattern Generation

    Direction ...Input or output Modes ...Internally or externally timed © National Instruments Corporation Level = 24 mA) — = 24 mA) 2.4 V outputs are tri-stated when logically high. Appendix A Specifications 0.4 V — (selectable) DIO 6533 User Manual...
  • Page 96 PXI-6533 32-bit input 16-bit input 8-bit input 32-bit output 16-bit output 8-bit output DIO 6533 User Manual Triton I Chip Set Triton II Chip Set Rates in MS/s (MB/s) on Sample Systems 2.8 (11.2) 4 (16) 4 (8) 5 (10) 6.67 (6.67)
  • Page 97 1400 (1400) — Rates in kS/s (kbytes/s) on Sample Systems 30 (120) 70 (280) 35 (70) 75 (150) 35 (35) 75 (75) Appendix A Specifications Natoma Chip Set — — — 140 (560) 165 (330) 165 (165) DIO 6533 User Manual...
  • Page 98 133 MHz Pentium computer with the Natoma (430HX) chip set. The DAQCard-6533 266 MHz Pentium II rates were measured using a 266 MHz Pentium II computer with the Natoma (440FX) chip set. DIO 6533 User Manual (max) PCI-DIO-32HS ...
  • Page 99 16-bit 44 (22) 8-bit 22 (22) Appendix A Specifications 133 MHz 266 MHz Pentium Pentium II 420 (105) 740 (185) 250 (125) 470 (235) 125 (125) 235 (235) depending on mode pattern mismatch on user-selected bits DIO 6533 User Manual...

  • Page 100: Power Requirement

    Dimensions, not including connectors ... 17.5 by 10.7 cm (6.9 by 4.2 in.) I/O connector DIO 6533 User Manual PCI-DIO-32HS, PXI-6533, and AT-DIO-32HS ... +4.65 to +5.25 VDC at 1 A DAQCard-6533 ... +4.65 to +5.25 VDC at 250 mA PCI-DIO-32HS, PXI-6533, and AT-DIO-32HS ...
  • Page 101 MIL-T-28800E and MIL-STD-810E Method 514. Test levels exceed those recommended in MIL-STD-810E for Category 1 (Basic Transportation, Figures 514.4-1 through 514.4-3). © National Instruments Corporation Appendix A Section 4.5.5.4.1) Half-sine shock pulse, 11 ms duration, 30 g peak, 30 shocks per face Specifications DIO 6533 User Manual...
  • Page 102 Optional Adapter Description This appendix describes an optional 68-to-50-pin DIO 6533 device adapter. The adapter changes the pinout of the 6533 device to match the pinout of an AT-DIO-32F device. The adapter enables you to use the 6533 device with cables, signal conditioning modules, and other accessories that require an AT-DIO-32F pinout.

  • Page 103: Figure B-1. 68-To-50-Pin Adapter Pin Assignments

    Appendix B Optional Adapter Description DIO 6533 User Manual DIOD1 DIOD4 DIOD0 DIOD3 DIOD6 DIOD7 DIOD5 DIOD2 DIOC7 DIOC5 11 12 DIOC1 DIOC3 13 14 DIOC0 DIOC2 15 16 DIOC4 DIOC6 17 18 ACK2 19 20 STOPTRIG2 (IN2) 21 22...

  • Page 104: Electronic Services

    Electronic Services Bulletin Board Support National Instruments has BBS and FTP sites dedicated for 24-hour support with a collection of files and documents to answer most common customer questions. From these sites, you can also download the latest instrument drivers, updates, and example programs. For recorded instructions on how to use the bulletin board and FTP services and for BBS automated information, call (512) 795-6990.

  • Page 105: Telephone And Fax Support

    Telephone and Fax Support National Instruments has branch offices all over the world. Use the list below to find the technical support number for your country. If there is no National Instruments office in your country, contact the source from which you purchased your software to obtain support.
  • Page 106 National Instruments for technical support helps our applications engineers answer your questions more efficiently. If you are using any National Instruments hardware or software products related to this problem, include the configuration forms from their user manuals. Include additional pages if necessary.

  • Page 107: Configuration Form

    Complete a new copy of this form each time you revise your software or hardware configuration, and use this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.
  • Page 108 Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs. Title: DIO 6533 User Manual Edition Date: July 1997 Part Number: 321464B-01 Please comment on the completeness, clarity, and organization of the manual.
  • Page 109 Prefix Meaning milli- µ- micro- nano- kilo- mega- Symbols ° degree negative of, or minus percent ± plus or minus positive of, or plus © National Instruments Corporation Value –3 –6 –9 Glossary DIO 6533 User Manual...
  • Page 110 Examples of PC buses are the AT, EISA, and PCI bus. Celsius clock hardware component that controls timing for reading from or writing to groups CMOS complementary metal-oxide semiconductor central processing unit CPULL control pullup/pulldown selection DIO 6533 User Manual © National Instruments Corporation...
  • Page 111 A port cannot belong to more than one group. digital trigger a TTL level signal having two discrete levels—a high and a low level— that starts or stops an operation digital input/output © National Instruments Corporation Glossary DIO 6533 User Manual...
  • Page 112 FIFO ahead of time. This again reduces the effect of latencies associated with getting the data from system memory to the DAQ device. DIO 6533 User Manual © National Instruments Corporation...
  • Page 113 CPU should suspend its current task to service a designated activity interrupt level the relative priority at which a device can interrupt © National Instruments Corporation Glossary DIO 6533 User Manual...
  • Page 114 1,024 words of memory LabVIEW laboratory virtual instrument engineering workbench latched digital I/O See strobed digital I/O. light-emitting diode least significant bit meters maximum megabytes of memory minimum min. minute most significant bit DIO 6533 User Manual , bytes/s © National Instruments Corporation...
  • Page 115 Intel to replace ISA and EISA. It is achieving widespread acceptance as a standard for PCs and work-stations; it offers a theoretical maximum transfer rate of 132 Mbytes/s. PCLK peripheral clock signal © National Instruments Corporation Glossary DIO 6533 User Manual...
  • Page 116 GPIB random-access memory request signal ribbon cable a flat cable in which the conductors are side by side DIO 6533 User Manual © National Instruments Corporation...
  • Page 117 RGND reserved ground root mean square RTSI Bus real-time system integration bus—the National Instruments timing bus that connects DAQ boards directly, by means of connectors on top of the boards, for precise synchronization of functions seconds samples settling time the amount of time required for a voltage to reach its final value within...
  • Page 118 If you connect two or more wired-OR outputs together, any one DIO 6533 User Manual G-10 © National Instruments Corporation...
  • Page 119 Microprocessors typically use 8, 16, or 32-bit words. working voltage the highest voltage that should be applied to a product in normal use, normally well under the breakdown voltage for safety margin © National Instruments Corporation G-11 Glossary DIO 6533 User Manual...
  • Page 120 PCLK reversed (figure), 5-32 bus interface specifications, A-8 change detection definition, 3-6 purpose and use, 3-7 to 3-8 clocks, board and RTSI, 4-8 configuration AT devices, 2-5 to 2-9 base I/O address selection, 2-6 DMA channel selection, 2-6 Index DIO 6533 User Manual...
  • Page 121 DIOA<0..7> signal description (table), 4-4 unstrobed I/O, 4-10 to 4-11 DIOB<0..7> signal description (table), 4-4 DIO 6533 User Manual unstrobed I/O, 4-10 to 4-11 DIOC<0..7> signal (table), 4-4 DIOD<0..7> signal (table), 4-4 DMA channel selection PC AT 16-bit DMA channel assignment...
  • Page 122 DAQCard-6533, 2-3 to 2-4 PCI-DIO-32HS, 2-1 to 2-2 PXI-6533, 2-2 to 2-3 software, 2-1 unpacking the DIO 6533, 1-8 interrupt channel selection, 2-6 to 2-9 PC AT 16-bit DMA channel assignment map (table), 2-9 PC AT I/O address map (table), 2-6 to 2-8...
  • Page 123 (figure), 5-21 output timing (figure), 5-22 manual. See documentation. message generation, 3-8 National Instruments application software, 1-4 to 1-5 NI-DAQ driver software, 1-5 to 1-6 noise, minimizing, 4-14 to 4-15 pattern generation change detection, 3-7 to 3-8...
  • Page 124 8255 emulation, 3-9 burst mode, 3-10 comparison of protocols, 3-10 to 3-11 leading-edge pulse, 3-9 level ACK, 3-9 long pulse, 3-9 trailing-edge pulse, 3-9 handshaking transfer controlling line polarities, 3-13 controlling startup sequence, 3-12 overview, 3-6 DIO 6533 User Manual...
  • Page 125 3-13 transmission line terminations (figure), 4-16 triggers RTSI triggers, 4-8 specifications RTSI triggers, A-7 start and stop triggers, A-7 two-way handshaking transfer. See handshaking transfer. unpacking the DIO 6533, 1-8 unstrobed I/O, 4-10 to 4-12 © National Instruments Corporation...

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