Lvtm Interface In Tmds Mode; Table 3-10 Lvtm Interface In Tmds Mode - AMD 780E Technical Reference Manual

LVTM Interface
Table 3-9 (Continued)
Pin Name
LVDS_BLON
LVDS_DIGON
LVDS_EN_BL
3.8.2

LVTM Interface in TMDS Mode

Table 3-10 LVTM Interface in TMDS Mode

Pin Name
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXOUT_L3N
TXOUT_L3P
TXOUT_U0N
TXOUT_U0P
© 2009 Advanced Micro Devices, Inc.
Proprietary
Power Ground
Type
Domain Domain
I/O VDD33 VSS
I/O VDD33 VSS
I/O VDD33 VSS
TMDS
Power
Functional Type
Domain
Name
TX0M O VDDLT18
TX0P O VDDLT18
TX1M O VDDLT18
TX1P O VDDLT18
TX2M O VDDLT18
TX2P O VDDLT18
TX3M O VDDLT18
TX3P O VDDLT18
TX4M O VDDLT18
TX4P O VDDLT18
Integrated
Functional Description
Termination
Digital panel backlight brightness control. Active high. It controls
backlight on/off or acts as PWM output to adjust brightness.
If LVTMA_BL_MOD_CNTL.LVTMA_BL_MOD_EN = 0, the pin
controls backlight on/off. Otherwise, it is the PWM output to adjust
the brightness.
LVTMA_BL_MOD_CNTL.LVTMA_BL_MOD_LEVEL can be used
to control the backlight level (256 steps) by means of pulse width
modulation. The duty cycle of the backlight signal can be set
through the LVTMA_BL_MOD_CNTL.LVTMA_BL_MOD_LEVEL
bits. For example, setting these bits to a value of 32 will set the
on-time to 32/256*(1/REF) and the off-time to
50k
(256-32)/256*(1/REF), where REF is the XTALIN frequency and is
programmable:
typically 14.318MHz or 100MHz.
PU/PD/none
Note that the PWM frequency is set by
LVTMA_BL_MOD_CNTL.LVTMA_BL_MOD_RES and
LVTMA_PWRSEQ_REF_DIV.LVTMA_BL_MOD_REF_DIV. The
PWM frequency =
REF/((BL_MOD_REF_DIV+1)*(BL_MOD_RES+1)).
For more information, refer to the RS780 Register Reference
Guide, order# 43451.
In CPIS mode, LVDS_BLON is VARY_BL as defined in CPIS.
PWM mode should be enabled. LVDS_EN_BL should be
connected to ENA_BL, which turns the backlight AC inverter
on/off.
50k
programmable: Control Panel Digital Power On/Off. Active high.
PU/PD/none
Enables Backlight for CPIS compliant LCD panels. Active high.
50k
Controlled by the hardware power up/down sequencer. For more
programmable:
details, refer to
PU/PD/none
Timing," on page 4- 5
Ground Integrated
Domain Termination
VSSLT None
VSSLT None
VSSLT None
VSSLT None
VSSLT None
VSSLT None
VSSLT None
VSSLT None
VSSLT None
VSSLT None
Figure 4-2, "LCD Panel Power Up/Down
.
Functional Description
TMDS data channel 0 (-)
TMDS data channel 0 (+)
TMDS data channel 1 (-)
TMDS data channel 1 (+)
TMDS data channel 2 (-)
TMDS data channel 2 (+)
TMDS data channel 3 (-). The channel is only used
in DVI dual-link mode and is not used for HDMI™
support.
TMDS data channel 3 (+). The channel is only used
in DVI dual-link mode and is not used for HDMI
support.
TMDS data channel 4 (-). The channel is only used
in DVI dual-link mode and is not used for HDMI
support.
TMDS data channel 4 (+) The channel is only used
in DVI dual-link mode and is not used for HDMI
support.
45732 AMD 780E Databook 3.10
3-9