Zenith H-100 Service Manual page 58

5-142
HLT
INDEX
INTRQ
Head load timing. The drive head is engaged when
this signal is high.
The index hole on the diskette has been detected.
Interrupt request. H-207 board has input for
the CPU.
LATE Write data bit late for drive precompensation.
MR Master reset pin on the 1797 Controller chip that
sets all registers in the chip to a known state.
pSTVAL* Status val id •
pSYNC New bus cycle may begin.
PD Pump down. Decreases the frequency of the raw
read data tracking clock.
PRECOMP Enables precompensation when low.
PU Pump up. Increases frequency of the raw read
data tracking clock.
pWR Valid data is on data-out bus (write bus).
RAWREAD Unprocessed data from the drive.
RCLK Clock that separates data from drive data and
clock stream.
RDD Data and clock stream from the drive.
RLME Data or status signals input for the bus are
enabled.
RDY Slave aboard is ready. (H-207 board is a slave
board. )
RE
READY
Read enable. Enables the 1797 chip for read
operations when low.
The 8" disk drive is ready.