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10-82
If the phase of RCLK should drift with respect to the
incoming ROO signal, U1 will send feedback pulses from U1-13
or Ul-14 to the VCO at U5.
These pulses will increase or
lower the VCO frequency.
In turn, the VCO frequency will
increase or decrease the RCLK frequency until it again in
phase with ROO.
Here's how:
If the frequency of RDD is higher than RCLK, then ROO
will go low at the beginning of RCLK.
The pump-up
output (PU) at U1-13 will go from a high-impedance
state to a logic one.
This increases the VCO frequency
which increases frequency of RCLK.
If the frequency of ROO is lower than RCLK, then RDO
will go low at the end of RCLK.
The pump-down output
(PO) responds by going from a high-impedance state
to logic zero.
This decreases the VCO frequency and
thus decreases the frequency of RCLK.
I f
RCLK and ROO are in phase, then PU and PO are in
a high-impedance state and the VCO frequency remains
constant.
Pins 5, 7, and 8 of u1 allow the 1797 to control clock
separation and data recovery.
When pins 7 and 8 are low,
the data recovery circuits are enabled.
If pin 7 is high,
which happens during a write operation, then the data
recovery circuits are disabled.
Pin 15, DOEN, controls the frequency of RCLK.
When pin
15 is log ic one, the frequency of RCLK is equal to the VCO
frequency divided by 16.
When pin 15 is logic zero, RCLK
is equal to the VCO frequency divided by 8.
DATA PRECOMPENSATION
Precompensation, used for 80-track double-density disk write
operations, places data properly on the disk so that it
can be read back wi th m'inimum error.
Error is introduced
by the shifting of old data that is adjacent to new data
being written.
This shifting is due to the nature of the
magnetic fields on the disk (like fields repel).
The precompensation circuits consist of U22, U1, and U3.
U22 sends the write data from pin 31 to U1-1.
U3 provides
delay timing for the write data in U1.
U22 selects the
amount of precompensation by setting the logic levels on
pin 18 (LATE) and pin 17 (EARLY),
5-137
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