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5-132
WRITE CONTROL LATCH (U30)
The control latch, U30, is written at the falling edge of
GLEN, which is the simultaneous assertion of pWR and the
YO output of the I/O address decoder.
The pWR signal comes
directly from the GPU, and the YO signal occurs when AO,
A1, and A2 are high, low, and high, respectively.
The YO
and pWR signal s are ORed at U21-6 to form GLEN.
The organization of each bit in the control latch is as
follows:
BIT
SIGNAL NAME
FUNCTION
0.1
DSA. DSB
00
=
select drive 1
10
=
select drive 3
01
=
select drive 2
11
=
select drive 4
2
8"/5"
0
=
sel ect 5.25"
1
=
select 8"
3
WEN
0
;;
deBt/hot. 1111
1
;;
/Seleot drive
drive.
.peoified by bit.
O.
1. and 2
4
PREC(}IP'
5.25" DDEN
0
=
precomp all
1
=
disable precomp
tracks
8" DDEN
0
=
precanp all
1
=
precomp tracks
tracks
44-76
5
5" FASTEP
0
=
1797 operates
1
=
1797 operates
as specified
in 8" mode
by bit 2
6
WAITEN
0
=
wait state
1
=
wait state
enable
enable
7
SDEN
0
=
double density
1
=
single density
'(Note:
Precomp is disabled in single density.)
When the WAITEN bit in the control latch is asserted, a
wait state is intitiated on the next read or write of the
data register.
WAITEN couples through U23. U26, and U32
to the 3-100 ROY line.
ROY goes low to put the GPU in a
wait state until the disk controller asserts ORQ at U22-38.
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