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10-82
1797 TIMING
U18. U12, U14, and U30 provide timing and control of timing
to the 1797.
Depending on the state of U14, the clock
frequency to U22-24 will be either 1 MHz or 2 MHz.
The operating frequency of the 1797 is automatically
switched from 1 MHz to 2 MHz when changing from 5-1/4"
drives to 8" drives.
This is done by U30-6 and is coupled
through U7-11 to the latch at U14.
One drawback of the 1797 is that it won't allow 5-1/4"
drives to step at a 3-mS rate during track seek.
To
circumvent this problem, U30-15 sets the 5" FASTSTEP
signal.
This signal couples through U7-12 to U14.
U14
increases the operating frequency to 2 MHz to speed up the
step rate.
At the end of the track-seek function, the clock
frequency is reduced to 1 MHz again for normal 5-1/4"
operation.
8" DRIVE INTERFACE
The 8" drive interface is through Plo
All output signals
to the drives are buffered through U8 and U10 except WG
and HLD.
The WG signal is sent through transistor Q2, as
described previously.
The HLD signal is inverted by U7-10
before being transmitted to the drives.
All input signals except READY and TWOSIDED are buffered
through the upper section of U9 when enabled by a high on
the 8"/5" line.
The READY signal is inverted at U6-6, while
the
n~OSIDED
signal is inverted at U6-11.
5" DRIVE INTERFACE
The 5" drive interface is through P2.
All output signals
to the drives are buffered through U10 and U11 except WG
and MOTOR.
The WG signal is sent through transistor Q3,
as described previously.
The MOTOR signal turns on the
disk drive motor whenever a logic zero is present at pins
9, 10, 12, and 13 of U23.
The single-shot at U15 keeps
the drive motor on for about 20 seconds after the disk
access is complete.
This provides a proper turn-off delay.
All input signals are buffered through the lower section
of U9, which is enabled by a low on the 8"/5" line.
5-139
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