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10-82
RDY DELAY
U19 is a quad flip-flop that acts as a delay line for the
DRQ signal from the 1797 to the S-100 RDY line.
The input
at U19-4, D1, is output at Q1 after one clock cycle.
Q1
is tied to D2 and is output to Q2 after another clock
cycle.
Q2 is also tied to U25-1 and D3.
From U25-12, the D2 signal presets flip-flop U26.
Flip-flop
U26 qualifies the FDSEL signal to enable read/write
operations in anticipation of the RDY line being made
active.
From D3 of U19, the delayed DRQ signal is output to Q3,
whic his connec ted to D4 and to jumper J 1, post G.
Post
Gis connected to po st F in 3 MHz operations, which do not
need additional delay of the DRQ signal.
Instead, the
output of Q4, which contains the DRQ signal delayed by three
to four clock cycles, is connected to jumper J1, post E.
For 6 MHz operation, J1 is connected between post E and
post F.
INTERRUPTS
There are two interrupts that the H-207 board can make.
They are the interrupt request (INTRQ) and the data request
(DRQ).
Both of these interrupts originate from the 1797.
The INTRQ signal is sent to indicate a command completion
or an error.
The DRQ signal is sent to indicate data will
be accepted in response to a disk read or write command.
The interrupts can be detected two ways, as either a
vectored interrupt on any of the bus interface pins from
4 to 11, or as a bit set in the status port, U31, which
can then be polled by the CPU.
The INTRQ signal pulls the bus out of a wait state caused
by a logic zero at U26-9.
When pin 39 of the 1797 asserts,
it is inverted at U25-6 to set pin 9 of U26.
5-135
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