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5-140
CALIBRATION CIRCUIT BOARD
The calibration circuit compares the end of the write pulse
with a narrow pulse of a known delay.
When the two happen
simultaneously, the LED on the calibration board is latched
on.
This indicates that the length of the write pulse is
properly ad justed •
The write pulse coming from CP3 is applied to NAND gate
U501D.
U501D inverts the pulse and applies it to inverter
U501C and to delay line DL501.
Within DL501 the pulse is
delayed 120 nS between pins 1 and 10 and 160 nS between
pi ns 1 and 6.
These two del ayed pul ses are then compared
by NAND gates U501A and U501B.
The result of the comparison
is a pul se 40 nS wid e and 120 nS del ayed in reference to
the write pul se .
If the write pulse has been adjusted for a 120 nS pulse
width, the write pulse at the D flip-flop U502B-11 will
go high when the 40 nS delayed pulse is low.
This condition
causes U502B to latch a low on the
Q
output, U502B-9.
A
low at this point turns on the LED, D501.
By adjusting the precompensation controls into this 40 nS
"window", it is possible to "tune" write precompensation
to be not only between 120 and 160 nS, but also much closer
to 120 nS than 160 nS.
To gain additional delay for greater write precompensation,
DL502 (optional HE 41-10) can be added to the circuit.
DL502 provides four additional delay taps with an additional
40 nS of delay per tap.
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