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5-138
Here's what happens ...
When the 1797 sends a data bit to U1-1, the strobe
line at U1-5 latches high.
This triggers U3-11 and
causes a negative-going pulse to ripple through
¢1,
~2,
¢3, and 94.
R3 sets the pulse width of these
signals and, therefore, the amount of precompensation.
With no precompensation (EARLY
=
LATE
=
0), the data
pulse is coupled to U1-6 at
~2
time.
If LATE
precompensation is selected, the data bit leaves U1-6
at ¢3 time.
EARLY precompensation synchronizes the
data bit to
¢T.
When ¢4 pulses low, it couples through U7 to U1-19
to clear the strobe at U1-5 in anticipation of the
next write data pulse.
Precompensation must be enabled for double-density
operation.
The CPU does this by setting U30-19 to logic
one and sending it to the DDEN input at U1-15.
The CPU
also asserts the PRECOMP line at U30-12.
This couples
through U6-8 to TG43 at U1-9.
TG43 must be high befure
precompensation can take place.
Even if PRECOMP isn't asserted, the write data should be
precompensated on the inner tracks, where the data is packed
closer together.
This condition is taken care of by U22-29,
which asserts on tracks greater than 43.
The TG43 signal
couples through U6-8 to the TG43 input of U1.
HEAD LOAD TIMING
The single-shot multivibrator at U15 provides read/write
head-load timing.
When the 1797 sends a head-load command,
pin 28 goes high to load the drive head and to trigger U15.
U15-7 goes low for about 50 mS.
This signal couples to
U22-23 to prevent a data read or write until U15 times out.
This delay compensates for bounce when the read/write head
contacts the disk surface.
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