Texas Instruments TMS320DM335 User Manual
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Texas Instruments TMS320DM335 User Manual

Texas Instruments TMS320DM335 User Manual

Digital media system-on-chip dmsoc arm subsystem
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TMS320DM335
Digital Media System-on-Chip (DMSoC)
ARM Subsystem
User's Guide
Literature Number: SPRUFX7
July 2008

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Summary of Contents for Texas Instruments TMS320DM335

  • Page 1 TMS320DM335 Digital Media System-on-Chip (DMSoC) ARM Subsystem User's Guide Literature Number: SPRUFX7 July 2008...
  • Page 2 SPRUFX7 – July 2008 Submit Documentation Feedback...

  • Page 3: Table Of Contents

    Contents ............................Preface ......................Introduction ......................... Device Overview ........................Block Diagram ....................ARM Subsystem in DM335 ..................ARM Subsystem Overview ................... Purpose of the ARM Subsystem ..................Components of the ARM Subsystem ........................References ........................ ARM Core ........................Introduction ...................... Operating States/Modes ....................
  • Page 4 www.ti.com ..........................PLLC2 ....................PLLC Functional Description ....................6.4.1 Multipliers and Dividers ......................6.4.2 Bypass Mode ......................... 6.4.3 PLL Mode ......................PLL Configuration ..................6.5.1 PLL Mode and Bypass Mode ................... 6.5.2 Changing Divider / Multiplier Ratios ..................6.5.3 PLL Power Down and Wakeup ....................
  • Page 5 www.ti.com ............7.7.6 Module Error Clear Register 1 (mod 32-41) (MERRCR1) ................7.7.7 Power Error Pending Register (PERRPR) ................7.7.8 Power Error Clear Register (PERRCR) ..............7.7.9 External Power Control Pending Register (EPCPR) ..............7.7.10 External Power Control Clear Register (EPCCR) ............
  • Page 6 www.ti.com ....................... 9.5.1 Timer64+ Control ...................... 9.5.2 USB PHY Control ................9.5.3 VPSS Clock and DAC Control and Status ................. 9.5.4 DDR I/O Timing Control and Status ..................Clock Out Configuration Status ..................... GIO De-Bounce Control ......................Power Management ....................9.8.1 Deep Sleep Control ....................
  • Page 7 www.ti.com ......................Boot Modes ....................... 11.1 Boot Modes Overview ........................ 11.1.1 Features .................... 11.1.2 Functional Block Diagram ...................... 11.2 ARM ROM Boot Modes ..................... 11.2.1 NAND Boot Mode ....................11.2.2 MMC/SD Boot Mode ..................... 11.2.3 UART Boot Mode ....................Power Management .........................
  • Page 8 www.ti.com List of Figures ....................Functional Block Diagram ..................ARM Subsystem Block Diagram ...................... Clocking Architecture ....................... PLLC1 Configuration ....................... PLLC2 Configuration ............... Clock Ratio Change and Alignment with Go Operation ....................Peripheral ID Register (PID) ..................PLL Control Register (PLLCTL) .................
  • Page 9 www.ti.com ..................8-12 Interrupt Enable Register 1 (EINT1) ............... 8-13 Interrupt Operation Control Register (INTCTL) ........................8-14 EABASE ................. 8-15 Interrupt Priority Register 0 (INTPRI0) ................. 8-16 Interrupt Priority Register 1 (INTPRI1) ................. 8-17 Interrupt Priority Register 2 (INTPRI2) ................. 8-18 Interrupt Priority Register 3 (INTPRI3) .................
  • Page 10 www.ti.com List of Tables ..................Exception Vector Table for ARM ................Different Address Types in ARM System ....................ITCM/DTCM Memory Map ....................ITCM/DTCM Size Encoding ..................... ETM Part Descriptions ........................ Memory Map ................ ARM Configuration Bus Access to Peripherals ...................... PLLC1 Output Clocks ......................
  • Page 11 www.ti.com ..................... AINTC Interrupt Connections ..................Interrupt Controller (INTC) Registers ..........Interrupt Status of INT[31:0] (if mapped to FIQ) Field Descriptions ..........Interrupt Status of INT[63:32] (if mapped to FIQ) Field Descriptions ..........Interrupt Status of INT[31:0] (if mapped to IRQ) Field Descriptions ..........
  • Page 12 www.ti.com ................ 11-5 MMC/SD UBL Signatures and Special Modes ....................11-6 UART Data Sequences ....................11-7 Host Utility Data Format ....................11-8 CRC32 Table Transfer ................... 12-1 Power Management Features List of Tables SPRUFX7 – July 2008 Submit Documentation Feedback...

  • Page 13: Preface

    Preface SPRUFX7 – July 2008 Read This First About This Manual This document describes the operation of the ARM subsystem in the TMS320DM335 Digital Media System-on-Chip (DMSoC). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.
  • Page 14 — TMS320DM335 Digital Media System-on-Chip (DMSoC) Inter-Integrated Circuit (I2C) Peripheral Reference Guide This document describes the inter-integrated circuit (I2C) peripheral in the TMS320DM335 Digital Media System-on-Chip (DMSoC). The I2C peripheral provides an interface between the DMSoC and other devices compliant with the I2C-bus specification and connected by way of an I2C-bus.
  • Page 15 — TMS320DM335 Digital Media System-on-Chip (DMSoC) Asynchronous External Memory Interface (EMIF) Reference Guide This document describes the asynchronous external memory interface (EMIF) in the TMS320DM335 Digital Media System-on-Chip (DMSoC). The EMIF supports a glueless interface to a variety of external devices.

  • Page 16: Introduction

    Introduction Device Overview The TMS320DM335 processor is a low cost, low power processor providing advanced graphical user interface for display applications that do not require video compression and decompression. Coupled with a video processing subsystem (VPSS) that provides 720p display, the DM335 processor is powered by a...

  • Page 17: Arm Subsystem In Dm335

    ARM Subsystem in DM335 www.ti.com The detailed block diagram is shown in Figure 1-1. Figure 1-1. Functional Block Diagram ARM Subsystem in DM335 The ARM926EJ-S 32-bit RISC processor in the ARMSS acts as the overall system controller. The ARM CPU performs general system control tasks, such as system initialization, configuration, power management, user interface, and user command implementation.

  • Page 18: Arm Subsystem Overview

    SPRUFX7 – July 2008 ARM Subsystem Overview Purpose of the ARM Subsystem The ARM Subsystem contains components required to provide the ARM926EJ-S (ARM) master control of the overall device system, including control over the VPSS Subsystem, the peripherals, and external memories.

  • Page 19: References

    References www.ti.com • Video Processing Front End (VPFE) – CCD Controller (CCDC) – Image Pipe (IPIPE) – H3A Engine (Hardware engine for computing Auto-focus, Auto white balance, and Auto exposure) – Multiply Mask / Lens Distortion Module (CFALD) • Video Processing Back End (VPBE) –...

  • Page 20: Arm Core

    SPRUFX7 – July 2008 ARM Core Introduction This chapter describes the ARM core and its associated memories. The ARM core consists of the following components: • ARM926EJ-S - 32-bit RISC processor • 16-KB Instruction cache • 8-KB Data cache • MMU •...

  • Page 21: Operating States/Modes

    Operating States/Modes www.ti.com Operating States/Modes The ARM can operate in two states: ARM (32-bit) mode and Thumb (16-bit) mode. You can switch the ARM926EJ-S processor between ARM mode and Thumb mode using the BX instruction. The ARM can operate in the following modes: •...

  • Page 22: Exceptions And Exception Vectors

    Exceptions and Exception Vectors www.ti.com Exceptions and Exception Vectors Exceptions arise when the normal flow of the program must be temporarily halted. The exceptions that occur in an ARM system are given below: • Reset exception: processor reset • FIQ interrupt: fast interrupt •...

  • Page 23: Coprocessor 15 (Cp15)

    Coprocessor 15 (CP15) www.ti.com a 16-bit architecture is its ability to manipulate 32-bit integers with single instructions, and to address a large address space efficiently. When processing 32-bit data, a 16-bit architecture takes at least two instructions to perform the same task as a single 32-bit instruction. However, not all of the code in a program processes 32-bit data (e.g., code that performs character string handling), and some instructions (like branches) do not process any data at all.

  • Page 24: 3.6.2 Memory Management Unit

    Coprocessor 15 (CP15) www.ti.com 3.6.2 Memory Management Unit The ARM926EJ-S MMU provides virtual memory features required by operating systems such as SymbianOS, WindowsCE, and Linux. A single set of two level page tables stored in main memory controls the address translation, permission checks, and memory region attributes for both data and instruction accesses.
  • Page 25 Coprocessor 15 (CP15) www.ti.com The write buffer is used for all writes to a non-cacheable bufferable region, write-through region, and write misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for cache line evictions or cleaning of dirty cache lines. The main write buffer has a 16-word data buffer and a four-address buffer.

  • Page 26: Tightly Coupled Memory

    Tightly Coupled Memory www.ti.com Tightly Coupled Memory The ARM926EJ-Shas a tightly coupled memory interface enabling separate instruction and data TCM to be interfaced to the ARM. TCMs are meant for storing real-time and performance critical code. The device supports both instruction TCM (I-TCM) and data TCM (D-TCM). The instruction TCM is located at 0x0000:0000 to 0x0000:7FFF.

  • Page 27: Embedded Trace Support

    Embedded Trace Support www.ti.com Write 0 to the ENB bit to enable ITCM and DTCM. Write 1 to the ENB bit to enable it. The physical address of the memory should be set to the ADDRESS field. The SIZE field reflects the size. The size encoding is given below in Table 3-4.
  • Page 28 Embedded Trace Support www.ti.com The ETM is used to compress the trace information and export it through a narrow trace port. An external Trace Port Analyzer (TPA) is used to capture the trace information. Note: Chapter 10 of the Embedded Trace Macro-cell Support of the ARM926EJ-S TRM, downloadable from http://www.arm.com for more detailed information.

  • Page 29: Memory Mapping

    SPRUFX7 – July 2008 Memory Mapping Memory Map The device memory map is shown in Table 4-1. The multiple columns represent the memory map of each of the masters on the chip. The ARM, EDMA, USB, and VPSS are all masters with access to the regions shown in the table.

  • Page 30: 4.1.1 Arm Internal Memories

    Memory Map www.ti.com 4.1.1 ARM Internal Memories The ARM has access to the following ARM internal memories: • 32KB ARM Internal RAM on TCM interface, logically separated into two 16KB pages to allow simultaneous access on any given cycle, if there are separate accesses for code (I-TCM bus) and data (D-TCM) to the different memory regions.

  • Page 31: Arm Configuration Bus Access To Peripherals

    Memory Map www.ti.com Table 4-2. ARM Configuration Bus Access to Peripherals Address Accessibility Region Start Size EDMA √ √ EDMA CC 0x01C0 0000 0x01C0 FFFF √ √ EDMA TC0 0x01C1 0000 0x01C1 03FF √ √ EDMA TC1 0x01C1 0400 0x01C1 07FF √...
  • Page 32 Memory Map www.ti.com Table 4-2. ARM Configuration Bus Access to Peripherals (continued) Address Accessibility √ √ Reserved 0x01E0 6400 0x01E0 FFFF √ √ ASYNC EMIF Control 0x01E1 0000 0x01E1 0FFF √ √ Multimedia / SD 0 0x01E1 1000 0x01E1 FFFF √...

  • Page 33: Memory Interfaces Overview

    Memory Interfaces Overview www.ti.com Memory Interfaces Overview This section describes the different memory interfaces. The device supports several memory and external device interfaces, including the following: • DDR2 / mDDR Synchronous DRAM • Asynchronous EMIF • NAND Flash • OneNAND flash 4.2.1 DDR2 EMIF The DDR2 EMIF interface, sometimes referred to as EMIF3.0 in the device documentation, is a dedicated interface to DDR and MDDR SDRAM.
  • Page 34 Memory Interfaces Overview www.ti.com 4.2.2.2 NAND (NAND, SmartMedia, xD) The NAND mode supports the following features: • NAND Flash on up to two asynchronous chip selects • Supports 8-bit and 16-bit data bus widths • Programmable cycle timings • Performs 1-bit and 4-bit ECC calculation (does not perform error correction) •...

  • Page 35: Device Clocking

    SPRUFX7 – July 2008 Device Clocking Overview The device requires one primary reference clock . The reference clock frequency may be generated either by crystal input or by external oscillator. The reference clock is the clock at the pins named MXI1/MXOI. The reference clock drives two separate PLL controllers (PLLC1 and PLLC2).

  • Page 36: Clocking Architecture

    Overview www.ti.com Figure 5-1. Clocking Architecture Device Clocking SPRUFX7 – July 2008 Submit Documentation Feedback...

  • Page 37: Peripheral Clocking Considerations

    • EXTCLK pin (external VPBE clock input pin) • PCLK pin (VPFE pixel clock input pin) For complete information on VPBE clocking, see the TMS320DM335 Digital Media System-on-Chip (DMSoC) Video Processing Back End (VPBE) Reference Guide (SPRUFX9). 5.2.2 USB Clocking The USB Controller is driven by two clocks: an output clock of PLL1 and an output clock of the USB Phy.

  • Page 38: Pll Controllers (Pllcs)

    SPRUFX7 – July 2008 PLL Controllers (PLLCs) PLL Controller Module Two PLL controllers provide clocks to different components of the chip. PLL controller 1 (PLLC1) provides clocks to most of the components of the chip. PLL controller 2 (PLLC2) provides clocks to the DDR PHY. As a module, the PLL controller provides the following: •...

  • Page 39: Pllc1

    PLLC1 www.ti.com PLLC1 PLLC1 provides most of the device clocks. Software controls PLLC1 operation through the PLLC1 registers. The following list, Table 6-1, and Figure 6-1 describe the customizations of PLLC1. • Provides primary device system clock • Software configurable •...

  • Page 40: Pllc1 Configuration

    PLLC2 www.ti.com Figure 6-1. PLLC1 Configuration PLLC2 PLLC2 provides the DDR PHY clock and CLKOUT3. Software controls PLLC2 operation through the PLLC2 registers. The following list, Table 6-2, and Figure 6-2 describe the customizations of PLLC2. • Provides DDR PHY clock and CLKOUT3 •...

  • Page 41: Pllc2 Configuration

    PLLC Functional Description www.ti.com Figure 6-2. PLLC2 Configuration CLKMODE PLLEN CLKIN Post-DIV Pre-DIV (/1) (programmable) SYSCLK1 OSCIN PLLDIV1 (/1) (DDR PHY) PLLM (programmable) SYSCLKBP BPDIV (/8) (CLKOUT3) PLLC Functional Description This section describes the multiplier and dividers in the PLL controller as well as the bypass and PLL modes of operation.
  • Page 42 PLL Configuration www.ti.com PLL Configuration This section describes the procedures for initializing and configuring the PLL controller. 6.5.1 PLL Mode and Bypass Mode 6.5.1.1 PLL Mode (PLLEN = 1) This section describes the sequence for PLL mode. 1. In PLLCTL, write CLKMODE = 0 (internal oscillator) or 1 (input clock) to select the type of reference clock.

  • Page 43: Clock Ratio Change And Alignment With Go Operation

    PLL Configuration www.ti.com 6.5.2.1.1 GO Operation Writes to the RATIO field in the PLLDIVn registers do not change the dividers’ actual divide ratios immediately. The PLLDIVn dividers only change to the new RATIO rates during a GO operation. This section discusses the GO operation and how the SYSCLKs are aligned. The PLL controller clock align control register (ALNCTL) determines which SYSCLKs must be aligned.

  • Page 44: Pll And Reset Controller Module Instance Table

    PLL Controller Register Map www.ti.com 6.5.2.2 Pre-Divider (PREDIV), PLL Multiplier (PLLM), and Post-Divider (POSTDIV) To change the values of PREDIV, PLLM, or POSTDIV; the PLL controller must first be placed in bypass mode. Perform the following steps to modify PREDIV, PLLM, or POSTDIV ratios. 1.
  • Page 45 PLL Controller Register Map www.ti.com Table 6-4. PLLC Registers (continued) Offset Acronym Register Description Section 138h PLLCMD PLL controller command register Section 6.6.11 13Ch PLLSTAT PLL controller status register Section 6.6.12 140h ALNCTL SYSCLKn divider ratio change and align control register Section 6.6.13 144h DCHANGE...

  • Page 46: Peripheral Id Register (Pid)

    PLL Controller Register Map www.ti.com 6.6.2 Peripheral ID Register (PID) The peripheral ID register (PID) is shown in Figure 6-4 and described in Table 6-5 for PLLC1 and PLLC2. Note that bit field descriptions shown in Figure 6-4 are given for PLLC1 (top) and PLLC2 (bottom). This format is used in the bit description figures throughout this section.

  • Page 47: Pll Control Register (Pllctl)

    PLL Controller Register Map www.ti.com 6.6.3 PLL Control (PLLCTL) The PLL control register is shown in Figure 6-5 and described in Table 6-6 for PLLC1 and PLLC2. Figure 6-5. PLL Control Register (PLLCTL) Reserved Reserved CLKMOD PLLSELB Reserved PLLENSR PLLDIS PLLRST Reserved PLLPWRDN...

  • Page 48: Pll Multiplier Control Register (Pllm)

    PLL Controller Register Map www.ti.com 6.6.4 PLL Multiplier Control Register (PLLM) The PLL multiplier control register (PLLM) is shown in Figure 6-6 and described in Table 6-7 for PLLC1 and PLLC2. For PLLC1, the default multiplier value is 180. For PLLC2, the default multiplier value is 92. You may change the multiplier value from 92 to 184.

  • Page 49: Pll Pre-Divider Control Register (Prediv)

    PLL Controller Register Map www.ti.com 6.6.5 PLL Pre-Divider Control Register (PREDIV) The PLL pre-divider control register (PREDIV) is shown in Figure 6-7 and described in Table 6-8 PLLC1 and PLLC2. For PLLC1, the pre-divider ratio is fixed (cannot be changed) to 8. For PLLC2, the pre-divider ratio defaults to 8, however, it may be changed to allow for lower frequencies.

  • Page 50: Pll Controller Divider 1 Register (Plldiv1)

    PLL Controller Register Map www.ti.com 6.6.6 PLL Controller Divider 1 Register (PLLDIV1) The PLL controller divider 1 register (PLLDIV1) is shown in Figure 6-8 and described in Table 6-9 PLLC1 and PLLC2. PLLDIV1 controls the divider for SYSCLK1. The divider for PLLC1 SYSCLK1 is fixed (cannot be changed) to (/2).

  • Page 51: Pll Controller Divider 2 Register (Plldiv2)

    PLL Controller Register Map www.ti.com 6.6.7 PLL Controller Divider 2 Register (PLLDIV2) The PLL controller divider 2 register (PLLDIV2) is shown in Figure 6-9 and described in Table 6-10 PLLC1 and PLLC2. PLLDIV2 controls the divider for SYSCLK2. The divider for PLLC1 SYSCLK2 is fixed (cannot be changed) to (/4).

  • Page 52: Pll Controller Divider 3 Register (Plldiv3)

    PLL Controller Register Map www.ti.com 6.6.8 PLL Controller Divider 3 Register (PLLDIV3) The PLL controller divider 3 register (PLLDIV3) is shown in Figure 6-10 and described in Table 6-11 PLLC1 and PLLC2. PLLDIV3 controls the divider for SYSCLK3. The divider for PLLC1 SYSCLK3 is programmable.

  • Page 53: Pll Post-Divider Control Register (Postdiv)

    PLL Controller Register Map www.ti.com 6.6.9 PLL Post-Divider Control Register (POSTDIV) The PLL post-divider control register (POSTDIV) is shown in Figure 6-11 and described in Table 6-12 PLLC1 and PLLC2. POSTDIV is a read only register. The post divider ratio for PLLC1 may be changed by the bit PLL1_POSTDIV in the miscellaneous control register (MISC) in the System Control module.

  • Page 54: Bypass Divider Register (Bpdiv)

    PLL Controller Register Map www.ti.com 6.6.10 Bypass Divider Register (BPDIV) The bypass divider register (BPDIV) is shown in Figure 6-12 and described in Table 6-13 for PLLC1 and PLLC2. BPDIV controls the divider for SYSCLKBP. The divider for PLLC1 SYSCLKBP is fixed (cannot be changed) to 3.

  • Page 55: Pll Controller Command Register (Pllcmd)

    PLL Controller Register Map www.ti.com 6.6.11 PLL Controller Command Register (PLLCMD) The PLL controller command register (PLLCMD) is shown in Figure 6-13 and described in Table 6-14 PLLC1 and PLLC2. PLLCMD is used to initiate a GO operation for SYSCLKn ratio change and/or phase alignment.

  • Page 56: Pll Controller Status Register (Pllstat)

    PLL Controller Register Map www.ti.com 6.6.12 PLL Controller Status Register (PLLSTAT) The PLL controller status register (PLLSTAT) is shown in Figure 6-14 and described in Table 6-15 PLLC1 and PLLC2. PLLSTAT shows the status of changing SYSCLKn divider ratios and/or phase alignment.

  • Page 57: Pll Controller Clock Align Control Register (Alnctl)

    PLL Controller Register Map www.ti.com 6.6.13 PLL Controller Clock Align Control Register (ALNCTL) The PLL controller clock align control register (ALNCTL) is shown in Figure 6-15 and described in Table 6-16 for PLLC1 and PLLC2. ALNCTL controls SYSCLK divider ratio change and alignment when GOSET bit in PLLCMD is set to 1.

  • Page 58: Plldiv Ratio Change Status (Dchange)

    PLL Controller Register Map www.ti.com 6.6.14 PLLDIV Ratio Change Status Register (DCHANGE) The PLLDIV ratio change status register (DCHANGE) is shown in Figure 6-16 and described in Table 6-17 for PLLC1 and PLLC2. Whenever a different ratio is written to the PLLDIVn registers, the PLLC flags the change in DCHANGE.

  • Page 59: Clock Enable Control Register (Cken)

    PLL Controller Register Map www.ti.com 6.6.15 Clock Enable Control Register (CKEN) The clock enable control register (CKEN) is shown in Figure 6-17 and described in Table 6-18 for PLLC1 and PLLC2. The CKEN register is used to enable the PLL auxiliary clock (AUXCLK). The auxiliary clock should always be enabled, so you must always set this bit to 1.

  • Page 60: Clock Status Register (Ckstat)

    PLL Controller Register Map www.ti.com 6.6.16 Clock Status Register (CKSTAT) The clock status (CKSTAT) register is shown in Figure 6-18 and described in Table 6-19 for PLLC1 and PLLC2. CKSTAT shows the on/off status of the bypass clock (SYSCLKBP) and the auxiliary clock (AUXCLK).

  • Page 61: Sysclk Status Register (Systat)

    PLL Controller Register Map www.ti.com 6.6.17 SYSCLK Status Register (SYSTAT) The SYSCLK status register (SYSTAT) is shown in Figure 6-19 and described in Table 6-20 for PLLC1 and PLLC2. SYSTAT shows the on/off status of the SYSCLKn clocks. Figure 6-19. SYSCLK Status Register (SYSTAT) Reserved SYSONn LEGEND: R = Read, n = value at reset...

  • Page 62: Pll Controller Divider 4 Register (Plldiv4)

    PLL Controller Register Map www.ti.com 6.6.18 PLL Controller Divider 4 Register (PLLDIV4) The PLL controller divider 4 register (PLLDIV4) is shown in Figure 6-20 and described in Table 6-21 PLLC1 and PLLC2. PLLDIV4 controls the divider for SYSCLK4. The divider for PLLC1 SYSCLK4 is programmable.

  • Page 63: Power And Sleep Controller (Psc)

    SPRUFX7 – July 2008 Power and Sleep Controller Introduction In the DM335 system, the Power and Sleep Controller (PSC) is responsible for managing transitions of system power on/off, clock on/off, and reset. A block diagram of the PSC is shown in Figure 7-1.
  • Page 64 Power Domain and Module Topology www.ti.com Figure 7-2. Power Domain and Module Topology Power and Sleep Controller SPRUFX7 – July 2008 Submit Documentation Feedback...

  • Page 65: Module Configuration

    Power Domain and Module Topology www.ti.com Table 7-1. Module Configuration Default States Module Module Name Power Domain Power Domain State Module State Number VPSS Master AlwaysOn SyncRst VPSS Slave AlwaysOn SyncRst EDMA (CC) AlwaysOn BTSEL[1:0] = 00 – Enable (NAND) BTSEL[1:0] = 01 –...

  • Page 66: 7.3.2 Module States

    Power Domain and Module States Defined www.ti.com Table 7-1. Module Configuration (continued) Default States AlwaysOn Enable AlwaysOn Enable AlwaysOn Enable AlwaysOn Enable AlwaysOn Enable AlwaysOn Enable AlwaysOn Enable AlwaysOn Enable Reserved Reserved Reserved Reserved VPSS DAC Always On SyncRst Power Domain and Module States Defined 7.3.1 Power Domain States A power domain can only be in one of two states: ON or OFF, defined as follows: •...
  • Page 67 Executing State Transitions www.ti.com The module states are defined as follows: Module State Module State Definition Enable A module in the enable state has its module reset de-asserted and it has its clock on. This is the normal run-time state for a given module. Disable A module in the disable state has its module reset de-asserted and it has its clock off.

  • Page 68: Icepick Emulation Commands

    PSC Interrupts www.ti.com Table 7-3. IcePick Emulation Commands (continued) Power On and Enable Features Power On and Enable Descriptions Reset Features Reset Descriptions Force Active Allows emulation to force the power Block Reset Allows emulation to block domain into an on state and force the software initiated local and module into the enable state.
  • Page 69 PSC Interrupts www.ti.com • When inhibit sleep is asserted by emulation and software attempts to transition the module out of the enable state • When force active is asserted by emulation and module is not already in the enable state 7.6.1.3 Local Reset Emulation Events A local reset emulation event occurs when emulation alters the local reset of a module.
  • Page 70 PSC Interrupts www.ti.com 7.6.3 Interrupt Handling Handle the PSC interrupts as described in the following procedure: First, enable the interrupt. 1. Set the EMUIHB bit in PDCTLx, the EMUIHB bit in MDCTL[x], and / or the EMURSTIE bit in MDCTL[x] to enable the interrupt events that you want.

  • Page 71: Psc Registers

    PSC Registers www.ti.com PSC Registers Table 7-5 lists the memory-mapped registers for the PSC. See the device memory map Table 4-2 for the memory address of these registers. The default, after reset, PSC configurations are shown in Table 7-1 Note: You must not read or write reserved PSC register fields.

  • Page 72: Peripheral Revision And Class Information Register (Pid)

    PSC Registers www.ti.com 7.7.1 Peripheral Revision and Class Information (PID) The peripheral revision and class information (PID) register is shown in Figure 7-3 and described in Table 7-6. Figure 7-3. Peripheral Revision and Class Information Register (PID) SCHEME Reserved FUNC R- 208 MAJOR CUSTOM...

  • Page 73: Interrupt Evaluation Register (Inteval)

    PSC Registers www.ti.com 7.7.2 Interrupt Evaluation Register (INTEVAL) The interrupt evaluation register (INTEVAL) is shown in Figure 7-4 and described in Table 7-7. Figure 7-4. Interrupt Evaluation Register (INTEVAL) Reserved ALLEV LEGEND: R = Read, W = Write, n = value at reset Table 7-7.

  • Page 74: Module Error Pending Register 0 (Mod 0 - 31) (Merrpr0)

    PSC Registers www.ti.com 7.7.3 Module Error Pending Register 0 (mod 0 - 31) (MERRPR0) The module error pending register 0 (mod 0 - 31) is shown in Figure 7-5 and described in Table 7-8. Figure 7-5. Module Error Pending Register 0 (mod 0 - 31) (MERRPR0) M0[32] LEGEND: R = Read, n = value at reset Table 7-8.

  • Page 75: Module Error Pending Register 1 (Mod 32-41) (Merrpr1)

    PSC Registers www.ti.com 7.7.4 Module Error Pending Register 1 (mod 32-41) (MERRPR1) The module error pending register 1 (mod 32 - 41) (MERRPR1) is shown in Figure 7-6 and described in Table 7-9. Figure 7-6. Module Error Pending Register 1 (mod 32-41) (MERRPR1) Reserved Reserved M[9]...

  • Page 76: Module Error Clear Register 0 (Mod 0-31) (Merrcr0)

    PSC Registers www.ti.com 7.7.5 Module Error Clear Register 0 (mod 0-31) (MERRCR0) The module error clear 0 (mod 0-31) register (MERRCR0) is shown in Figure 7-7 and described in Table 7-10. Figure 7-7. Module Error Clear Register 0 (mod 0-31) (MERRCR0) M0[32] LEGEND: R = Read, n = value at reset Table 7-10.

  • Page 77: Module Error Clear Register 1 (Mod 32-41) (Merrcr1)

    PSC Registers www.ti.com 7.7.6 Module Error Clear Register 1 (mod 32-41) (MERRCR1) The module error clear 1 (mod 32-41) register (MERRCR1) is shown in Figure 7-8 and described in Table 7-11. Figure 7-8. Module Error Clear Register 1 (mod 32-41) (MERRCR1) Reserved Reserved M[9]...

  • Page 78: Power Error Pending Register (Perrpr)

    PSC Registers www.ti.com 7.7.7 Power Error Pending Register (PERRPR) The power error pending register (PERRPR) is shown in Figure 7-9 and described in Table 7-12. Figure 7-9. Power Error Pending Register (PERRPR) Reserved P[1] LEGEND: R = Read, n = value at reset Table 7-12.

  • Page 79: Power Error Clear Register (Perrcr)

    PSC Registers www.ti.com 7.7.8 Power Error Clear Register (PERRCR) The power error clear register (PERRCR) is shown in Figure 7-10 and described in Table 7-13. Figure 7-10. Power Error Clear Register (PERRCR) Reserved P[1] LEGEND: R = Read, W = Write, n = value at reset Table 7-13.

  • Page 80: External Power Control Pending Register (Epcpr)

    PSC Registers www.ti.com 7.7.9 External Power Control Pending Register (EPCPR) The external power control pending register (EPCPR) is shown in Figure 7-11 and described in Table 7-14. Figure 7-11. External Power Control Pending Register (EPCPR) Reserved EPC[1] LEGEND: R = Read, n = value at reset Table 7-14.

  • Page 81: External Power Control Clear Register (Epccr)

    PSC Registers www.ti.com 7.7.10 External Power Control Clear Register (EPCCR) The external power control clear register (EPCCR) is shown in Figure 7-12 and described in Table 7-15. Figure 7-12. External Power Control Clear Register (EPCCR) Reserved EPC[1] LEGEND: R = Read, W = Write, n = value at reset Table 7-15.

  • Page 82: Power Domain Transition Command Register (Ptcmd)

    PSC Registers www.ti.com 7.7.11 Power Domain Transition Command Register (PTCMD) The power domain transition command register (PTCMD) is shown in Figure 7-13 and described in Table 7-16. Figure 7-13. Power Domain Transition Command Register (PTCMD) Reserved GO[1] LEGEND: R = Read, W = Write, n = value at reset Table 7-16.

  • Page 83: Power Domain Transition Status Register (Ptstat)

    PSC Registers www.ti.com 7.7.12 Power Domain Transition Status Register (PTSTAT) The power domain transition status register (PTSTAT) is shown in Figure 7-14 and described in Table 7-17 Figure 7-14. Power Domain Transition Status Register (PTSTAT) Reserved GOSTAT[1] LEGEND: R = Read, n = value at reset Table 7-17.

  • Page 84: Power Domain Status N Register (Pdstatn)

    PSC Registers www.ti.com 7.7.13 Power Domain Status Register 0 (PDSTATn) The power domain status n register (PDSTATn) is shown in Figure 7-15 and described in Table 7-18. Figure 7-15. Power Domain Status n Register (PDSTATn) Reserved Reserved EMUIHB Reserved PORDONE Reserved STATE LEGEND: R = Read;...

  • Page 85: Power Domain Control N Register (Pdctln)

    PSC Registers www.ti.com 7.7.14 Power Domain Control n Register 0 (PDCTLn) The power domain control n register (PDCTLn) is shown in Figure 7-16 and described in Table 7-19. In the device, only PDCTL0 is applicable because there is only one power domain, the AlwaysOn power domain.

  • Page 86: Module Status N Register (Mdstatn)

    PSC Registers www.ti.com 7.7.15 Module Status n Register 0-32 (MDSTATn) The module status 0 register (MDSTATn) is shown in Figure 7-17 and described in Table 7-20. See Table 7-1 for after reset default module states. Figure 7-17. Module Status n Register (MDSTATn) Reserved EMUIHB EMURST...

  • Page 87: Module Control N Register 0-41 (Mdctln)

    PSC Registers www.ti.com 7.7.16 Module Control n Register 0-51 (MDCTLn) The module control n register 0-41 (MDCTLn) is shown in Figure 7-18 and described in Table 7-21. See Table 7-1 for after reset default module states. It is not possible to change the module states for modules 29 through 38.

  • Page 88: Aintc Interrupt Connections

    SPRUFX7 – July 2008 Interrupt Controller Introduction The device ARM Interrupt Controller (AINTC) has the following features: • Supports up to 64 interrupt channels (16 external channels) • Interrupt mask for each channel • Each interrupt channel is mappable to a Fast Interrupt Request (FIQ) or to an Interrupt Request (IRQ) type of interrupt.
  • Page 89 INTC Methodology www.ti.com Table 8-1. AINTC Interrupt Connections (continued) Interrupt Acronym Source Interrupt Acronym Source Number Number VPSSINT5 VPSS - INT5 PWMINT1 PWM 1 VPSSINT6 VPSS - INT6 PWMINT2 PWM2 VPSSINT7 VPSS - INT7 I2CINT VPSSINT8 VPSS - INT8 UARTINT0 UART0 Reserved UARTINT1...

  • Page 90: Aintc Functional Diagram

    INTC Methodology www.ti.com • The INTC generates the entry address of the pending interrupt with the highest priority and stores the entry address in the FIQENTRY or the IRQENTRY register, depending on whether the interrupt is mapped to IRQ or FIQ interrupt. The IRQ or FIQ ISR can then read the entry address and its branch to the ISR of the interrupt.

  • Page 91: Interrupt Entry Table

    INTC Methodology www.ti.com 8.3.3 Vector Table Entry Address Generation To help speed up the ISR, the AINTC provides two vectors into the ARM’s interrupt entry table, which correspond to the highest priority effective IRQ and FIQ interrupts. This vector is generated by modifying a base address with a priority index.

  • Page 92: Immediate Interrupt Disable / Enable

    INTC Methodology www.ti.com 8.3.5 Enabling and Disabling Interrupts The AINTC has two methods for enabling and disabling interrupts: immediate or delayed, based on the setting of the IDMODE bit in the INTCTL register. When 0 (default), clearing an interrupt's EINT bit has an immediate effect.

  • Page 93: Interrupt Controller (Intc) Registers

    INTC Registers www.ti.com INTC Registers Table 8-2 lists the memory-mapped registers for the INTC. See the device memory mapTable 4-2 for the memory address of these registers. Table 8-2. Interrupt Controller (INTC) Registers Offset Acronym Register Description Section FIQ0 Interrupt Status of INT [31:0] (if mapped to FIQ) Section 8.4.1 FIQ1 Interrupt Status of INT [63:32] (if mapped to FIQ)

  • Page 94: Interrupt Status Of Int[31:0] (If Mapped To Fiq)

    INTC Registers www.ti.com 8.4.1 Fast Interrupt Request Status Register 0 (FIQ0) The fast interrupt request status register 0 (FIQ0) is shown in Figure 8-5 and described in Table 8-3. Figure 8-5. Interrupt Status of INT[31:0] (if mapped to FIQ) FIQ[31:0] R/W-1 LEGEND: R/W = Read/Write;...

  • Page 95: Interrupt Status Of Int[63:32] (If Mapped To Fiq)

    INTC Registers www.ti.com 8.4.2 Fast Interrupt Request Status Register 1 (FIQ1) The fast interrupt request status register 1 (FIQ1) is shown in Figure 8-6 and described in Table 8-4. Figure 8-6. Interrupt Status of INT[63:32] (if mapped to FIQ) FIQ[63:32] R/W-1 LEGEND: R/W = Read/Write;...

  • Page 96: Interrupt Status Of Int[31:0] (If Mapped To Irq)

    INTC Registers www.ti.com 8.4.3 Interrupt Request Status Register 0 (IRQ0) The interrupt request status register 0 (IRQ0) is shown in Figure 8-7 and described in Table 8-5. Figure 8-7. Interrupt Status of INT[31:0] (if mapped to IRQ) IRQ[31:0] R/W-1 LEGEND: R/W = Read/Write; n = value at reset Table 8-5.

  • Page 97: Interrupt Status Of Int[31:0] (If Mapped To Irq)

    INTC Registers www.ti.com 8.4.4 Interrupt Request Status Register 1 (IRQ1) The interrupt request status register 1 (IRQ1) is shown in Figure 8-8 and described in Table 8-6. Figure 8-8. Interrupt Status of INT[31:0] (if mapped to IRQ) IRQ[63:32] R/W-1 LEGEND: R/W = Read/Write; n = value at reset Table 8-6.

  • Page 98: Fast Interrupt Request Entry Address Register (Fiqentry)

    INTC Registers www.ti.com 8.4.5 Fast Interrupt Request Entry Address Register (FIQENTRY) The fast interrupt request entry address register (FIQENTRY) is shown in Figure 8-9 and described in Table 8-7. Figure 8-9. Fast Interrupt Request Entry Address Register (FIQENTRY) FIQENTRY LEGEND: R = Read only; n = value at reset Table 8-7.

  • Page 99: Interrupt Request Entry Address Register (Irqentry)

    INTC Registers www.ti.com 8.4.6 Interrupt Request Entry Address Register (IRQENTRY) The interrupt request entry address register (IRQENTRY) is shown in Figure 8-10 and described in Table 8-8. Figure 8-10. Interrupt Request Entry Address Register (IRQENTRY) IRQENTRY LEGEND: R = Read only; n = value at reset Table 8-8.

  • Page 100: Interrupt Enable Register 0 (Eint0)

    INTC Registers www.ti.com 8.4.7 Interrupt Enable Register 0 (EINT0) The interrupt enable register 0 (EINT0) is shown in Figure 8-11 and described in Table 8-9. Figure 8-11. Interrupt Enable Register 0 (EINT0) EINT[31:0] R/W-0 LEGEND: R/W = Read/Write; n = value at reset Table 8-9.

  • Page 101: Interrupt Enable Register 1 (Eint1)

    INTC Registers www.ti.com 8.4.8 Interrupt Enable Register 1 (EINT1) The interrupt enable register 1 (EINT1) is shown in Figure 8-12 and described in Table 8-10. Figure 8-12. Interrupt Enable Register 1 (EINT1) EINT[63:32] R/W-0 LEGEND: R/W = Read/Write; n = value at reset Table 8-10.

  • Page 102: Interrupt Operation Control Register (Intctl)

    INTC Registers www.ti.com 8.4.9 Interrupt Operation Control Register (INTCTL) The interrupt operation control register (INTCTL) is shown in Figure 8-13 and described in Table 8-11. Figure 8-13. Interrupt Operation Control Register (INTCTL) Reserved IDMODE IERAW FERAW R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write, R = Read only; n = value at reset Table 8-11.

  • Page 103: Eabase Field Descriptions

    INTC Registers www.ti.com 8.4.10 EABASE The EABASE register is shown in Figure 8-14 and described in Table 8-12. Figure 8-14. EABASE Reserved EABASE Reserved SIZE R/W-0 R/W-0 LEGEND: R/W = Read/Write, R = Read only; n = value at reset Table 8-12.

  • Page 104: Interrupt Priority Register 0 (Intpri0)

    INTC Registers www.ti.com 8.4.11 Interrupt Priority Register 0 (INTPRI0) The interrupt priority register 0 (INTPRI0) is shown in Figure 8-15 and described in Table 8-13. Figure 8-15. Interrupt Priority Register 0 (INTPRI0) Reserved INT7 Reserved INT6 Reserved INT5 Reserved INT4 R/W-7 R/W-7 R/W-7...

  • Page 105: Interrupt Priority Register 1 (Intpri1)

    INTC Registers www.ti.com 8.4.12 Interrupt Priority Register 1 (INTPRI1) The interrupt priority register 1 (INTPRI1) is shown in Figure 8-16 and described in Table 8-14. Figure 8-16. Interrupt Priority Register 1 (INTPRI1) Reserved INT15 Reserved INT14 Reserved INT13 Reserved INT12 R/W-7 R/W-7 R/W-7...

  • Page 106: Interrupt Priority Register 2 (Intpri2)

    INTC Registers www.ti.com 8.4.13 Interrupt Priority Register 2 (INTPRI2) The interrupt priority register 2 (INTPRI2) is shown in Figure 8-17 and described in Table 8-15. Figure 8-17. Interrupt Priority Register 2 (INTPRI2) Reserved INT23 Reserved INT22 Reserved INT21 Reserved INT20 R/W-7 R/W-7 R/W-7...

  • Page 107: Interrupt Priority Register 3 (Intpri3)

    INTC Registers www.ti.com 8.4.14 Interrupt Priority Register 3 (INTPRI3) The interrupt priority register 3 (INTPRI3) is shown in Figure 8-18 and described in Table 8-16. Figure 8-18. Interrupt Priority Register 3 (INTPRI3) Reserved INT31 Reserved INT30 Reserved INT29 Reserved INT28 R/W-7 R/W-7 R/W-7...

  • Page 108: Interrupt Priority Register 4 (Intpri4)

    INTC Registers www.ti.com 8.4.15 Interrupt Priority Register 4 (INTPRI4) The interrupt priority register 4 (INTPRI4) is shown in Figure 8-19 and described in Table 8-17. Figure 8-19. Interrupt Priority Register 4 (INTPRI4) Reserved INT39 Reserved INT38 Reserved INT37 Reserved INT36 R/W-7 R/W-7 R/W-7...

  • Page 109: Interrupt Priority Register 5 (Intpri5)

    INTC Registers www.ti.com 8.4.16 Interrupt Priority Register 5 (INTPRI5) The interrupt priority register 5 (INTPRI5) is shown in Figure 8-20 and described in Table 8-18. Figure 8-20. Interrupt Priority Register 5 (INTPRI5) Reserved INT47 Reserved INT46 Reserved INT45 Reserved INT44 R/W-7 R/W-7 R/W-7...

  • Page 110: Interrupt Priority Register 6 (Intpri6)

    INTC Registers www.ti.com 8.4.17 Interrupt Priority Register 6 (INTPRI6) The interrupt priority register 6 (INTPRI6) is shown in Figure 8-21 and described in Table 8-19. Figure 8-21. Interrupt Priority Register 6 (INTPRI6) Reserved INT55 Reserved INT54 Reserved INT53 Reserved INT52 R/W-7 R/W-7 R/W-7...

  • Page 111: Interrupt Priority Register 7 (Intpri7)

    INTC Registers www.ti.com 8.4.18 Interrupt Priority Register 7 (INTPRI7) The interrupt priority register 7 (INTPRI7) is shown in Figure 8-22 and described in Table 8-20. Figure 8-22. Interrupt Priority Register 7 (INTPRI7) Reserved INT63 Reserved INT62 Reserved INT61 Reserved INT60 R/W-7 R/W-7 R/W-7...

  • Page 112: Device Configuration

    SPRUFX7 – July 2008 System Control Module Overview of the System Control Module The device’s system control module is a system-level module containing status and top-level control logic required by the device. The system control module consists of a miscellaneous set of status and control registers, accessible the ARM and supporting all of the following system features and operations: •...
  • Page 113 ARM Interrupt and EDMA Event Multiplexing Control www.ti.com 9.3.1.1 Hardware Controlled Default Pin Multiplexing There are configuration input signals that can set some of the default pin mux and hardware configurations that may be needed for device boot. Use pins AECFG[3:0] to configure the pins of the AEMIF.
  • Page 114 Clock Out Configuration Status www.ti.com 9.5.2 USB PHY Control The USB_PHY_CTL register controls various features of the USB PHY, as shown in Figure 9-14 Table 9-17. 9.5.3 VPSS Clock and DAC Control and Status Clocks for the video processing subsystem are controlled via the VPSS_CLK_CTRL register. Video DAC configuration is controlled by VDAC.

  • Page 115: Master Ids

    Bandwidth Management www.ti.com Bandwidth Management 9.9.1 Bus Master DMA Priority Control In order to determine allowed connections between masters and slaves, each master request source must have a unique master ID (mstid) associated with it. The master ID for each device master is shown in Table 9-1.

  • Page 116: Default Master Priorities

    Bandwidth Management www.ti.com Prioritization within each switched central resource (SCR) is selected to be either fixed or dynamic. Dynamic prioritization is based on an incoming priority signal from each master. On the device, only the VPSS and EDMA masters actually generate priority values. For all other masters, the value is programmed in the chip-level MSTRPRI registers.

  • Page 117: System Module (Sys) Registers

    System Control Register Descriptions www.ti.com 9.10 System Control Register Descriptions 9.10.1 Introduction Table 9-3 lists the memory-mapped registers for the System Module (SYS). See the device memory map Table 4-2 the memory address of these registers. Table 9-3. System Module (SYS) Registers Offset Acronym Register Description...

  • Page 118: Pinmux0 - Pin Mux 0 (Video In) Pin Mux Register

    System Control Register Descriptions www.ti.com 9.10.2 PINMUX0 - Pin Mux 0 (Video In) Pin Mux Register The PINMUX0 register controls pin multiplexing for the VPFE pins. Figure 9-1. PINMUX0 - Pin Mux 0 (Video In) Pin Mux Register Reserved Reserved Reserved PCLK CAM_WEN...
  • Page 119 System Control Register Descriptions www.ti.com Table 9-4. PINMUX0 - Pin Mux 0 (Video In) Pin Mux Register Field Descriptions (continued) Field Value Description CIN_4 Enable the CIN[4] (Video In Pin Mux) GIO[98] CIN[4] SPI[2]_SDI SPI[2]_SDENA[1] YCIN_5 Enable the CIN[5] (Video In Pin Mux) GIO[99] CIN[5] SPI[2]_SDENA[0]...

  • Page 120: Pinmux1 - Pin Mux 1 (Video Out) Pin Mux Register

    System Control Register Descriptions www.ti.com 9.10.3 PINMUX1 - Pin Mux 1 (Video Out) Pin Mux Register The PINMUX1 register controls pin multiplexing for the VPBE pins. Figure 9-2. PINMUX1 - Pin Mux 1 (Video Out) Pin Mux Register Reserved VCLK EXTCLK FIELD DLCD...
  • Page 121 System Control Register Descriptions www.ti.com Table 9-5. PINMUX1 - Pin Mux 1 (Video Out) Pin Mux Register Field Descriptions (continued) Field Value Description 11-10 COUT_2 Enable COUT[2] (Video Out Pin Mux) GIO[76] COUT[2] PWM2 RTO3 COUT_3 Enable COUT[3] (Video Out Pin Mux) GIO[77] COUT[3] PWM2...

  • Page 122: Pinmux2 - Pin Mux 2 (Aemif) Pin Mux Register

    System Control Register Descriptions www.ti.com 9.10.4 PINMUX2 - Pin Mux 2 (AEMIF) Pin Mux Register The PINMUX2 register controls pin multiplexing for the AEMIF pins. Some of the register fields have default values set by external pins that allow control of the AEMIF configuration to match the boot mode. Figure 9-3.
  • Page 123 System Control Register Descriptions www.ti.com Table 9-6. PINMUX2 - Pin Mux 2 (AEMIF) Pin Mux Register Field Descriptions (continued) Field Value Description EM_D15_8 Enable EM_D[15:8] (AEMIF Pin Mux) Reset value set by AECFG[3] - sets AEMIF bus width for boot OneNAND operation requires PINMUX2[4:1] = AECFG[3:0] = 0010b;...

  • Page 124: Pinmux3 - Pin Mux 3 (Gio/Misc) Pin Mux Register Field Descriptions

    System Control Register Descriptions www.ti.com 9.10.5 PINMUX3 - Pin Mux 3 (GIO/Misc) Pin Mux Register The PINMUX3 register controls pin multiplexing for the GIO pins. Figure 9-4. PINMUX3 - Pin Mux 3 (GIO/Misc) Pin Mux Register Reserved GIO7 GIO8 GIO9 GIO10 GIO11 GIO12 GIO13 GIO14 GIO15 GIO16 GIO17 GIO18 R/W-0 R/W-0...
  • Page 125 System Control Register Descriptions www.ti.com Table 9-7. PINMUX3 - Pin Mux 3 (GIO/Misc) Pin Mux Register Field Descriptions (continued) Field Value Description GIO17 Enable GIO[17](GPIO Pin Mux) GIO[17] CLKOUT2 GIO18 Enable GIO[18](GPIO Pin Mux) GIO[18] CLKOUT1 15-14 GIO19 Enable GIO[19](GPIO Pin Mux) GIO[19] SD1_DATA0 UART2_TXD...

  • Page 126: Pinmux3 - Pin Mux 3 (Gio/Misc) Pin Mux Register

    System Control Register Descriptions www.ti.com Table 9-7. PINMUX3 - Pin Mux 3 (GIO/Misc) Pin Mux Register Field Descriptions (continued) Field Value Description GIO30 Enable GIO[30](GPIO Pin Mux) GIO[30] ASP0_DX System Control Module SPRUFX7 – July 2008 Submit Documentation Feedback...

  • Page 127: Pinmux4 - Pin Mux 4 (Misc) Pin Mux Register

    System Control Register Descriptions www.ti.com 9.10.6 PINMUX4 - Pin Mux 4 (Misc) Pin Mux Register The PINMUX4 register controls pin multiplexing for SPI0 and MMC/SD0. Figure 9-5. PINMUX4 - Pin Mux 4 (Misc) Pin Mux Register Reserved MMCSD0_MS SPI0_SDI SPI0_SDENA R/W-0 R/W-0 R/W-0...

  • Page 128: Bootcfg - Boot Configuration

    System Control Register Descriptions www.ti.com 9.10.7 BOOTCFG - Boot Configuration The device boot configuration (the state of the BTSEL[1:0] and AECFG[3:0] signals are captured in the BOOTCFG register. Figure 9-6. BOOTCFG - Boot Configuration Reserved Reserved GIO0_RESET BTSEL Reserved AECFG R-1101 LEGEND: R = Read only;...

  • Page 129: Arm_Intmux - Arm Interrupt Mux Control Register

    System Control Register Descriptions www.ti.com 9.10.8 ARM_INTMUX - ARM Interrupt Mux Control Register The ARM_INTMUX register provides multiplexing control for interrupts to the ARM since the Interrupt Controller (INTC) can only support 64 discrete events. Figure 9-7. ARM_INTMUX - ARM Interrupt Mux Control Register Reserved Reserved INT20...

  • Page 130: Edma_Evtmux - Edma Event Mux Control Register

    System Control Register Descriptions www.ti.com 9.10.9 EDMA_EVTMUX - EDMA Event Mux Control Register The EDMA_EVTMUX register controls multiplexing for EDMA Events due to the limited number of events supported by the EDMA. Figure 9-8. EDMA_EVTMUX - EDMA Event Mux Control Register Reserved EVT26 EVT9...

  • Page 131: Ddr_Slew - Ddr Slew

    System Control Register Descriptions www.ti.com 9.10.10 DDR_SLEW - DDR Slew The DDR_SLEW registers allows firmware control of the DDR Slew Rate. Figure 9-9. DDR_SLEW - DDR Slew Reserved Reserved DDRDATA_SLEW DDRCMD_SLEW LEGEND: R = Read only; -n = value after reset Table 9-12.

  • Page 132: Clkout - Clkout Div/Out Control

    System Control Register Descriptions www.ti.com 9.10.11 CLKOUT - CLKOUT Divisor / Output Control The CLKOUT register provides control of divisors and output enables for CLKOUT[3:1]. In the device, this register is read only. The CLKOUT[3:1] pins are multiplexed. Use the PINMUX3 register in the system control module to control the pin multiplexing for CLKOUT[3:1].

  • Page 133: Device_Id - Device Id

    Value Description 31-28 DEVREV 0-7h Device Revision 27-12 PARTNUM 0-FFFFh Part Number/Device JTAG ID (Uniquely Defined) 11-1 MFGR 0-7FFh Manufacturer's JTAG ID Texas Instruments' Mfg ID RESERVED Reserved (Always 1) SPRUFX7 – July 2008 System Control Module Submit Documentation Feedback...

  • Page 134: Vdac_Config - Video Dac Configuration

    System Control Register Descriptions www.ti.com 9.10.13 VDAC_CONFIG - Video Dac Configuration the VDAC_CONFIG register provides control of the Video DAC. Figure 9-12. VDAC_CONFIG - Video Dac Configuration Reserved TRESB4R4 TRESB4R2 R/W-0xC R/W-0x8 TRESB4R2 TRESB4R1 TRIMBITS R/W-0x8 R/W-0xC R/W-0x37 TRIMBITS PWD_BGZ SPEED TVINT R/W-0x37...

  • Page 135: Timer64_Ctl - Timer64+ Input Control

    System Control Register Descriptions www.ti.com 9.10.14 TIMER64_CTL - Timer64+ Input Control The TIMER64_CTL register provides Timer64+ input control. Figure 9-13. TIMER64_CTL - Timer64+ Input Control Reserved GIO3_4 GIO1_2 R/W-0 R/W-0 LEGEND: R/W = Read/Write, R = Read only; n = value at reset Table 9-16.

  • Page 136: Usb_Phy_Ctrl - Usb Phy Control

    System Control Register Descriptions www.ti.com 9.10.15 USB_PHY_CTRL - USB PHY Control The USB_PHY_CTL register controls various features of the USB PHY. Figure 9-14. USB_PHY_CTRL - USB PHY Control Reserved Reserved Reserved DATAPOL PHYCLKSRC PHYCLKGD R/W-0 R/W-0 SESNDEN VBDTCTEN VBUSENS PHYPLLON Reserved VPSS_OSCPDWN OTGPDWN...
  • Page 137 System Control Register Descriptions www.ti.com Table 9-17. USB_PHY_CTRL - USB PHY Control Field Descriptions (continued) Field Value Description VPSS_OSCPDW VPSS oscillator power down control VPSS MXI2 powered VPSS MXI2 power off OTGPDWN USB OTG analog block power down control OTG analog block powered OTG analog block power off PHYPDWN USB PHY power down control...

  • Page 138: Misc - Miscellaneous Control

    System Control Register Descriptions www.ti.com 9.10.16 MISC - Miscellaneous Control The MISC register include miscellaneous control functions. Figure 9-15. MISC - Miscellaneous Control Reserved Reserved TIMER2_WDT DEV_SPEED PLL1_POSTDIV AIM_WAIST R/W-1 R-eFuse R/W-1 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 9-18.

  • Page 139: Master Priorities 1(Mstpri1) Register

    System Control Register Descriptions www.ti.com 9.10.18 Master Priorities 1 (MSTPRI1) Register The master priorities 1 (MSTPRI1) register is shown in Figure 9-17 and discussed in Table 9-20. It provides control of the bus masters' DMA priorities. Figure 9-17. Master Priorities 1(MSTPRI1) Register Reserved USBP Reserved...

  • Page 140: Vpss_Clk_Ctrl - Vpss Clock Mux Control

    System Control Register Descriptions www.ti.com 9.10.19 VPSS_CLK_CTRL - VPSS Clock Mux Control The VPSS Clock multiplexing control is provided by the VPSS_CLK_CTRL register. Figure 9-18. VPSS_CLK_CTRL - VPSS Clock Mux Control Reserved Reserved VENC_CLK_SRC DACCLKEN VENCLKEN PCLK_INV VPSS_MUXSEL R/W-0 R/W-0 R/W-0 R/W-0 R/W-0...

  • Page 141: Deep Sleep Mode Configuration (Deepsleep) Register

    System Control Register Descriptions www.ti.com 9.10.20 Deep Sleep Mode Configuration (DEEPSLEEP) Register The deep sleep mode configuration (DEEPSLEEP) register is shown in Figure 9-19 and described in Table 9-22 Figure 9-19. Deep Sleep Mode Configuration (DEEPSLEEP) Register SLEEPENABLE SLEEPCOMPLETE Reserved R/W-0 COUNT Reserved...

  • Page 142: Debounce[8] - De-Bounce For Gio[N] Input

    System Control Register Descriptions www.ti.com 9.10.21 DEBOUNCE[8] - De-bounce for GIO[n] Input The DEBOUNCE[8] array of registers provide the controls for enabling and configuring Debounce for GIO[7:0] inputs. Figure 9-20. DEBOUNCE[8] - De-bounce for GIO[n] Input ENABLE Reserved INTERVAL R/W-0 R/W-0 LEGEND: R/W = Read/Write, R = Read only;...

  • Page 143: Vtp Io Control Register (Vtpiocr)

    9.10.22 VTPIOCR - VTP IO Control Register VTPIOCR is used to calibrate the DDR2/mDDR I/O's. For information on how to calibrate the DDR2/mDDR I/O's using this register, refer to the TMS320DM335 DDR2/mDDR Peripheral Reference Guide (SPRUFZ2). Figure 9-21. VTP IO Control Register (VTPIOCR)

  • Page 144: Reset Types

    SPRUFX7 – July 2008 Reset 10.1 Reset Overview There are five types of reset in the device. The types of reset differ by how they are initiated and/or by their effect on the chip. Each type is briefly described in Table 10-1 and further described in the following sections.
  • Page 145 Types of Reset www.ti.com 10.3 Types of Reset 10.3.1 Power-On Reset (POR) POR totally resets the chip, including all modules, memories, and emulation circuitry. The following steps describe the POR sequence: 1. Apply power and clocks to the chip and drive TRSTN and RESETN low to initiate POR. 2.
  • Page 146 Max reset may be blocked by an emulator command. This allows an emulator to block a WDT initiated max reset for debug purposes. For information on the WDT, see the TMS320DM335 Digital Media System-on-Chip (DMSoC) Timer / Watchdog Timer Reference Guide (SPRUFY0) . See Chapter 3 for information on IcePick emulation.
  • Page 147 Default Device Configurations www.ti.com Note: The device configuration pins are multiplexed with AEMIF pins. After the device configuration pins are sampled at reset, they automatically change to function as AEMIF pins. Pin multiplexing is described in Chapter Table 10-3. Device Configuration Default Setting Device (by internal...
  • Page 148 Boot modes are further described in Chapter 10.4.5 AEMIF Configuration For more information on the AEMIF, see the TMS320DM335 Digital Media System-on-Chip (DMSoC) Asynchronous External Memory Interface (EMIF) Reference Guide (SPRUFZ1) 10.4.5.1 AEMIF Pin Configuration The input pins AECFG[3:0] determine the AEMIF configuration immediately after reset. Use AECFG[3:0] to properly configure the pins of the AEMIF.
  • Page 149 SPRUFX7 – July 2008 Boot Modes 11.1 Boot Modes Overview The device ARM can boot from either Async EMIF (AEMIF/OneNand) or from ARM ROM, as determined by the setting of the device configuration pins BTSEL[1:0]. The BTSEL[1:0] pins can define the ROM boot mode further as well.

  • Page 150: Boot Modes Overview

    Boot Modes Overview www.ti.com – Supports NAND flash that requires chip select to stay low during the tR read time • ARM ROM Boot - MMC/SD Mode – No support for a full firmware boot. Instead, copies a second stage Uwer Boot Loader (UBL) from MMC/SD to ARm Internal RAM (AIM) and transfers control to the user software.

  • Page 151: Boot Mode Functional Block Diagram

    ARM ROM Boot Modes www.ti.com 11.1.2 Functional Block Diagram The general boot sequence is shown in Figure 11-2. Figure 11-2. Boot Mode Functional Block Diagram Reset Boot mode Internal ROM Boot mode Boot from Boot from UART NAND flash Boot OK ? Boot OK ? Boot from MMC/SD...

  • Page 152: Nand Boot Flow

    ARM ROM Boot Modes www.ti.com If a valid UBL is not found here, as determined by reading a valid UBL magic number, the next block is searched. Searching continues for up to 24 blocks. This provision for additional searching is made in case the first few consecutive blocks have been marked as bad (i.e., they have errors).

  • Page 153: Nand Ubl Descriptor

    ARM ROM Boot Modes www.ti.com The NAND User boot loader UBL descriptor format is described in Table 11-1. Table 11-1. NAND UBL Descriptor Page 0 Address 32-Bits Description 0xA1AC EDxx Magic number (0xA1ACEDxx) Entry Point Address of UBL Entry point address for the user boot-loader (absolute address) Number of pages in UBL Number of pages (size of user boot-loader in number of pages) Starting Block # of UBL...
  • Page 154 ARM ROM Boot Modes www.ti.com Figure 11-4. 4-Bit ECC Format and Bit 10 to 8-Bit Compression Algorithm Algorithm to store 10 bit codes in 8 bit words Data //Convert eight 10-bit codes to ten 8-bit words: Syndrome0 = syndromes10[0] & 0xFF; Syndrome1 = ((syndromes10[1] &...
  • Page 155 ARM ROM Boot Modes www.ti.com Figure 11-5. 4-Bit ECC Format for 2048+64 Byte Page Size Data 512+16 byte Syndrome Data 512+16 byte 1 Page Syndrome (2048+64 Data byte) 512+16 byte Syndrome Data 512+16 byte Syndrome 11.2.1.1 NAND Boot Detailed Flow An overview of the NAND Boot process is shown in the flow chart in Figure 11-6 and exemplified in...

  • Page 156: Nand Boot Mode Flow Chart

    ARM ROM Boot Modes www.ti.com • May be the same block as UBL descriptor – Starting Page of UBL • May not be the same page as UBL descriptor since full pages must be loaded • Copy the User boot-loader from NAND flash to IRAM with hardware ECC error detection enabled. If a 4-bit ECC read error is detected, the UBL will correct the error via the ECC correction algorithm.

  • Page 157: Arm Nand Rom Boot Loader Example

    ARM ROM Boot Modes www.ti.com Figure 11-7. ARM NAND ROM Boot Loader Example Page Block CIS/IDI Found magic number User boot loader (UBL) definition 32-bits Page 0 addr UBL magic number ID 0xA1ACED00 Page Block UBL Def Entry point addr of UBL 0x00002100 UBL start addr Number of pages in UBL...

  • Page 158: Descriptor Search For Arm Nand Boot Mode

    ARM ROM Boot Modes www.ti.com Figure 11-8. Descriptor Search for ARM NAND Boot Mode Page 0 Block CIS/IDI Page 0 Block Start searching at Block 1, Page 0 If no magic number found or Page 0 Block NAND read error detected If no magic number found or Page 0 Block...
  • Page 159 ARM ROM Boot Modes www.ti.com Table 11-3. NAND IDs Supported (continued) Number of pages per Bytes per page Block shift value Device ID block (including extra data) (For address) No. of address cycles 0xE6 512+16 0x39 512+16 0x6B 512+16 0x73 512+16 0x33 512+16...

  • Page 160: Mmc/Sd Boot Mode Overview

    ARM ROM Boot Modes www.ti.com The MMC/SD RBL will use the hardware CRC error detection capability to determine if a read error occurs when reading the UBL including the UBL descriptor. If a read error occurs, the UBL copy will immediately halt for that instance of magic number but the RBL will continue to search the block following that block in which the magic number was found for another instance of a magic number.

  • Page 161: Mmc/Sd Ubl Descriptor

    ARM ROM Boot Modes www.ti.com The MMC/SD User boot loader UBL descriptor format is described in Table 11-4. Table 11-4. MMC/SD UBL Descriptor Page 0 Address 32-Bits Description 0xA1AC EDxx Magic number (0xA1ACEDxx) Entry Point Address of UBL Entry point address for the user boot-loader (absolute address) Number of blocks in UBL Number of blocks (size of user boot-loader in number of blocks) Starting Block # of UBL...

  • Page 162: Mmc/Sd Boot Mode Flow Chart

    ARM ROM Boot Modes www.ti.com Figure 11-10. MMC/SD Boot Mode Flow Chart MMC/SD boot mode Start searching for valid magic number block M=1. Read block M If a failure has occured, read next consecutive (M++) block up to M=24 Magic number OK When a valid UBL signature is found, the Write block...

  • Page 163: Arm Mmc/Sd Rom Boot Loader Example

    ARM ROM Boot Modes www.ti.com Figure 11-11. ARM MMC/SD ROM Boot Loader Example User boot loader (UBL) definition Found magic number Byte addr 32-bits Block UBL def 0xA1ACED00 UBL magic number ID Entry point addr of UBL 0x00002100 UBL start addr UBL block 1 0x00000013 19 blocks...

  • Page 164: Descriptor Search For Arm Mmc/Sd Boot Mode

    ARM ROM Boot Modes www.ti.com Figure 11-12. Descriptor Search for ARM MMC/SD Boot Mode Start searching at block 0 Block If no magic number found or MMC/SD read error detected Block If no magic number found or MMC/SD read error detected Block If no magic number found or MMC/SD read error detected...

  • Page 165: Uart Boot Mode Handshake

    ARM ROM Boot Modes www.ti.com 11.2.3.1 Serial Host Handshake If the state of BTSEL[1:0] pins reset is 11, then the UART boot mode executes as shown in Figure 11-13. The state of BTSEL[1:0] pins at reset is captured and stored in the bits BTSEL in the BOOTCFG register in the System Control module.

  • Page 166: Uart Data Sequences

    ARM ROM Boot Modes www.ti.com 11.2.3.2 UART Boot Loader Data Sequences The serial bootloader data sequences consist of handshake messages, UBL header, and the UBL payload itself. The messages use a fixed 8-byte ASCII string including a null string terminator. Short messages have leading spaces besides the null.

  • Page 167: Host Utility Timing

    ARM ROM Boot Modes www.ti.com Table 11-7. Host Utility Data Format "^^^^ACK/0" Transfer Start Byte ——→ "^" "^" "^" "^" "A" "C" "K" "/0" Checksum "9af944c9" Transfer ——→ Table 11-8. CRC32 Table Transfer crc32_table[1024] = {0x01234567L, 0x89ABCDEFL..} Start Byte ——→ "0"...

  • Page 168: Power Management Features

    SPRUFX7 – July 2008 Power Management 12.1 Overview The device is designed for minimal power consumption. There are two components to power consumption: active power and leakage power. Active power is the power consumed to perform work and scales with clock frequency and the amount of computations being performed. Active power can be reduced by controlling the clocks in such a way as to either operate at a clock setting just high enough to complete the required operation in the required timeline or to run at a clock setting until the work is complete and then drastically cut the clocks (e.g., to PLL bypass mode) until additional work must be...
  • Page 169 Clock Management www.ti.com 12.3 Clock Management 12.3.1 Module Clock Disable The module clock disable feature allows software to disable individual module clocks, in order to reduce a module's active power consumption to 0. The device is designed in full static CMOS; thus, when a module clock stops, the module's state is preserved.
  • Page 170 You can power-down the USB Phy when it is not in use. The USB Phy is powered-down via the PHYPWDN bit in the USB_PHY_CTL register of the system control module. USB_PHY_CTL is described Chapter Also, see the TMS320DM335 DMSoC Universal Serial Bus (USB) Controller Reference Guide (SPRUFY9) for more information. Power Management SPRUFX7 –...
  • Page 171 Furthermore, you can use the DACCLKEN in register VPSS_CLK_CTRL to disable each DAC clock. See the TMS320DM335 Video Processing Back End (VPBE) Peripheral Reference Guide (SPRUFX9) for detailed information on DAC power-down. 12.6.3 DDR Self-Refresh and Power Down The DDR controller supports self-refresh and power down.
  • Page 172 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

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