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Renesas 89HPES24T3G2ZCALI User Manual (165 pages)

PCI Express Switch

Brand: Renesas | Category: Switch | Size: 1 MB

About this Manual
3
Content Summary
3
Signal Nomenclature
3
Numeric Representations
4
Data Units
4
Register Terminology
5
Use of Hypertext
6
Reference Documents
6
Revision History
6
Table of Contents
9
PES24T3G2 Device Overview
21
Introduction
21
Features
21
Table 1.1 Table
23
Logic Diagram - PES24T3G2
24
Vendor ID
24
Device ID
25
Revision ID
25
Jtag ID
25
Ssid/Ssvid
25
PES24T3G2 Device ID
25
Pin Description
26
Table 1.3 PCI Express Interface Pins
26
Table 1.4 Smbus Interface Pins
26
Table 1.5 General Purpose I/O Pins
27
Table 1.6 System Pins
28
Table 1.7 Test Pins
28
Table 1.8 Power, Ground, and Serdes Resistor Pins
29
Pin Characteristics
30
Table 1.9 Pin Characteristics
30
Port Configuration
31
Figure 1.3 PES24T3G2 Port Configuration
31
Clocking, Reset and Initialization
33
Clocking
33
Initialization
33
Table 2.1 Boot Configuration Vector Signals
33
Reset
34
Fundamental Reset
34
Figure 2.1 Fundamental Reset with Serial EEPROM Initialization
36
Hot Reset
37
Figure 2.2 Fundamental Reset Using RSTHALT to Keep Device in Quasi-Reset State
37
Upstream Secondary Bus Reset
38
Downstream Secondary Bus Reset
38
Downstream Port Reset Outputs
39
Power Enable Controlled Reset Output
39
Figure 2.3 Power Enable Controlled Reset Output Mode Operation
39
Power Good Controlled Reset Output
40
Figure 2.4 Power Good Controlled Reset Output Mode Operation
40
Link Operation
41
Introduction
41
Polarity Inversion
41
Lane Reversal
41
Link Width Negotiation
42
Figure 3.1 Merged Port Lane Reversal
42
Dynamic Link Width Reconfiguration
43
Dynamic Link Width Reconfiguration Support in the PES24T3G2
43
Link Speed Negotiation
44
Link Speed Negotiation in the PES24T3G2
44
Software Management of Link Speed
45
Link Reliability
45
Link Retraining
45
Autonomous Link Reliability Management
46
Link down
48
Slot Power Limit Support
48
Upstream Port
48
Downstream Port
48
Link States
48
Active State Power Management
49
Figure 3.2 PES24T3G2 ASPM Link Sate Transitions
49
Link Status
50
De-Emphasis Negotiation
50
Low-Swing Transmitter Voltage Mode
50
Crosslink
50
General Purpose I/O
51
Introduction
51
GPIO Configuration
51
GPIO Pin Configured as an Input
51
Table 4.1 General Purpose I/O Pin Alternate Function
51
Table 4.2 GPIO Pin Configuration
51
GPIO Pin Configured as an Output
52
GPIO Pin Configured as an Alternate Function
52
Smbus Interfaces
53
Introduction
53
Figure 5.1 Smbus Interface Configuration Examples
53
Master Smbus Interface
54
Initialization
54
Serial EEPROM
54
Table 5.1 Serial EEPROM Smbus Address
54
Table 5.2 PES24T3G2 Compatible Serial Eeproms
55
Figure 5.2 Single Double Word Initialization Sequence Format
55
Figure 5.3 Sequential Double Word Initialization Sequence Format
56
Figure 5.4 Configuration Done Sequence Format
56
Table 5.3 Serial EEPROM Initialization Errors
58
I/O Expanders
59
Table 5.4 I/O Expander Function Allocation
59
Table 5.5 I/O Expander Default Output Signal Value
60
Table 5.6 I/O Expander 0 Signals
63
Table 5.7 I/O Expander 2 Signals
63
Slave Smbus Interface
64
Table 5.8 I/O Expander 4 Signals
64
Initialization
65
Smbus Transactions
65
Table 5.9 Slave Smbus Address When a Static Address Is Selected
65
Table 5.10 Slave Smbus Command Code Fields
65
Figure 5.5 Slave Smbus Command Code Format
65
Table 5.11 CSR Register Read or Write Operation Byte Sequence
66
Table 5.12 CSR Register Read or Write CMD Field Description
67
Table 5.13 Serial EEPROM Read or Write Operation Byte Sequence
67
Figure 5.6 CSR Register Read or Write CMD Field Format
67
Table 5.14 Serial EEPROM Read or Write CMD Field Description
68
Figure 5.7 Serial EEPROM Read or Write CMD Field Format
68
Figure 5.8 CSR Register Read Using Smbus Block Write/Read Transactions with PEC Disabled
69
Figure 5.9 Serial EEPROM Read Using Smbus Block Write/Read Transactions with PEC
69
Figure 5.10 CSR Register Write Using Smbus Block Write Transactions with PEC Disabled
70
Figure 5.11 Serial EEPROM Write Using Smbus Block Write Transactions with PEC Disabled
70
Figure 5.12 Serial EEPROM Write Using Smbus Block Write Transactions with PEC Enabled
70
Figure 5.13 CSR Register Read Using Smbus Read and Write Transactions with PEC Disabled
71
Power Management
73
Introduction
73
Figure 6.1 PES24T3G2 Power Management State Transition Diagram
73
PME Messages
74
PCI-Express Power Management Fence Protocol
74
Table 6.1 PES24T3G2 Power Management State Transition Diagram
74
Power Budgeting Capability
75
Hot-Plug and Hot-Swap
77
Hot-Plug
77
Figure 7.1 Hot-Plug on Switch Downstream Slots Application
77
Figure 7.2 Hot-Plug with Switch on Add-In Card Application
78
Figure 7.3 Hot-Plug with Carrier Card Application
78
Hot-Plug I/O Expander
80
Hot-Plug Interrupts and Wake-Up
80
Legacy System Hot-Plug Support
81
Hot-Swap
82
Figure 7.4 PES24T3G2 Hot-Plug Event Signalling
82
Configuration Registers
83
Configuration Space Organization
83
Table 8.1 Base Addresses for Port Configuration Space Register
83
Upstream Port (Port 0)
84
Table 8.2 Upstream Port 0 Configuration Space Registers
84
Figure 8.1 Port Configuration Space Organization
84
Downstream Ports
88
Table 8.3 Downstream Ports 2, 4, and 6 Configuration Space Registers
88
Register Definitions
92
Type 1 Configuration Header Registers
92
PCI Express Capability Structure
102
Power Management Capability Structure
118
Message Signaled Interrupt Capability Structure
119
Subsystem ID and Subsystem Vendor ID
121
Extended Configuration Space Access Registers
121
Advanced Error Reporting (AER) Enhanced Capability
122
Device Serial Number Enhanced Capability
130
PCI Express Virtual Channel Capability
131
Power Budgeting Enhanced Capability
137
Switch Control and Status Registers
138
Autonomous Link Reliability Management
153
JTAG Boundary Scan
157
Introduction
157
Test Access Point
157
Signal Definitions
157
Figure 9.1 Diagram of the JTAG Logic
157
Table 9.1 JTAG Pin Descriptions
158
Figure 9.2 State Diagram of Pes24T3G2'S TAP Controller
158
Boundary Scan Chain
159
Table 9.2 Boundary Scan Chain
159
Test Data Register (DR)
160
Boundary Scan Registers
160
Figure 9.3 Diagram of Observe-Only Input Cell
160
Figure 9.4 Diagram of Output Cell
161
Figure 9.5 Diagram of Bidirectional Cell
161
Instruction Register (IR)
162
Extest
162
Table 9.3 Instructions Supported by Pes24T3G2'S JTAG Boundary Scan
162
Sample/Preload
163
Bypass
163
Clamp
163
Idcode
163
Table 9.4 System Controller Device Identification Register
163
Figure 9.6 Device ID Register Format
163
Validate
164
Reserved
164
Usage Considerations
164

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