Epson S1D13806 Series Manuals

Manuals and User Guides for Epson S1D13806 Series. We have 1 Epson S1D13806 Series manual available for free PDF download: Technical Manual

Epson S1D13806 Series Technical Manual (471 pages)

Embedded DRAM Graphics Controller

Brand: Epson | Category: Video Card | Size: 3 MB

Evaluation Board
3
Hardware Functional Specification
4
Programming Notes and Examples
4
Table of Contents
6
Introduction
13
Scope
13
Overview Description
13
Features
14
Table 2-1 S1D13806 Features
14
System Implementation
15
Figure 3-1 Typical System Diagram (Generic Bus)
15
Figure 3-2 Typical System Diagram (Hitachi SH-4 Bus)
15
Typical System Implementation Diagrams
16
Figure 3-3 Typical System Diagram (Hitachi SH-3 Bus)
16
Figure 3-4 Typical System Diagram (MC68K Bus 1, Motorola 16-Bit 68000)
16
Figure 3-5 Typical System Diagram (MC68K Bus 2, Motorola 32-Bit 68030)
17
Figure 3-6 Typical System Diagram (Motorola Power PC Bus)
17
Figure 3-7 Typical System Diagram (NEC MIPS Vr41Xx Bus)
18
Figure 3-8 Typical System Diagram (PC Card Bus)
18
Figure 3-9 Typical System Diagram (Philips MIPS PR31500/PR31700 Bus)
19
Figure 3-10 Typical System Diagram (Toshiba MIPS Tx39Xx Bus)
19
Pins
20
Pinout Diagram
20
Figure 4-1 Pinout Diagram 144-Pin QFP20 Surface Mount Package
20
Pin Description
21
Host Interface
22
Table 4-1 Host Interface Pin Descriptions
22
LCD Interface
26
Mediaplug Interface
26
Table 4-2 LCD Interface Pin Descriptions
26
Table 4-3 Mediaplug Pin Description
26
CRT Interface
27
General Purpose IO
27
Table 4-4 CRT Interface Pin Descriptions
27
Table 4-5 General Purpose IO Pin Descriptions
27
Configuration
28
Miscellaneous
28
Table 4-6 Configuration Pin Descriptions
28
Table 4-7 Miscellaneous Interface Pin Descriptions
28
Summary of Configuration Options
29
Table 4-8 Summary of Power-On/Reset Options
29
Multiple Function Pin Mapping
30
Table 4-9 CPU Interface Pin Mapping
30
Table 4-10 LCD Interface Pin Mapping
31
CRT/TV Interface
32
Figure 4-2 External Circuitry for CRT Interface
32
Table 5-1 Absolute Maximum Ratings
33
Table 5-2 Recommended Operating Conditions
33
Table 5-3 Electrical Characteristics for VDD = 3.3V Typical
34
C. Characteristics
35
Clock Timing
35
Input Clocks
35
Figure 6-1 Clock Input Requirement
35
Table 6-1 Clock Input Requirements for CLKI, CLKI2, and CLKI3
35
Internal Clocks
36
Table 6-2 Clock Input Requirements for CLKI, CLKI2, and CLKI3 When Divided down for MCLK
36
Table 6-3 Clock Input Requirements for CLKI, CLKI2, and CLKI3 When Divided down for LCD PCLK, CRT/TV PCLK, or Mediaplug Clock
36
Table 6-4 Internal Clock Requirements
36
CPU Interface Timing
37
Generic Interface Timing
37
Figure 6-2 Generic Interface Timing
37
Table 6-5 Generic Interface Timing
38
Hitachi SH-4 Interface Timing
39
Figure 6-3 Hitachi SH-4 Interface Timing
39
Table 6-6 Hitachi SH-4 Interface Timing
40
Hitachi SH-3 Interface Timing
41
Figure 6-4 Hitachi SH-3 Interface Timing
41
Table 6-7 Hitachi SH-3 Interface Timing
42
MIPS/ISA Interface Timing (E.g. NEC Vr41Xx)
43
Figure 6-5 MIPS/ISA Interface Timing
43
Table 6-8 MIPS/ISA Interface Timing
44
Motorola MC68K Bus 1 Interface Timing (E.g. MC68000)
45
Figure 6-6 Motorola MC68K Bus 1 Interface Timing
45
Table 6-9 Motorola MC68K Bus 1 Interface Timing
46
Motorola MC68K Bus 2 Interface Timing (E.g. MC68030)
47
Figure 6-7 Motorola MC68K Bus 2 Interface Timing
47
Table 6-10 Motorola MC68K Bus 2 Interface Timing
48
Motorola Powerpc Interface Timing (E.g. Mpc8Xx, MC68040, Coldfire)
49
Figure 6-8 Motorola Powerpc Interface Timing
49
Table 6-11 Motorola Powerpc Interface Timing
50
PC Card Timing (E.g. Strongarm)
51
Figure 6-9 PC Card Timing
51
Table 6-12 PC Card Timing
52
Philips Interface Timing (E.g. PR31500/PR31700)
53
Figure 6-10 Philips Interface Timing
53
Toshiba Interface Timing (E.g. Tx39Xx)
55
Figure 6-11 Toshiba Interface Timing
55
Power Sequencing
57
LCD Power Sequencing
57
Figure 6-12 LCD Panel Power-Off/Power-On Timing
57
Power Save Status
58
Figure 6-13 Power Save Status Bits and Local Bus Memory Access Relative to Power Save Mode
58
Display Interface
59
Single Monochrome 4-Bit Panel Timing
59
Figure 6-14 Single Monochrome 4-Bit Panel Timing
59
Figure 6-15 Single Monochrome 4-Bit Panel A.C. Timing
60
Single Monochrome 8-Bit Panel Timing
61
Figure 6-16 Single Monochrome 8-Bit Panel Timing
61
Figure 6-17 Single Monochrome 8-Bit Panel A.C. Timing
62
Single Color 4-Bit Panel Timing
63
Figure 6-18 Single Color 4-Bit Panel Timing
63
Figure 6-19 Single Color 4-Bit Panel A.C. Timing
64
Single Color 8-Bit Panel Timing (Format 1)
65
Figure 6-20 Single Color 8-Bit Panel Timing (Format 1)
65
Figure 6-21 Single Color 8-Bit Panel A.C. Timing (Format 1)
66
Single Color 8-Bit Panel Timing (Format 2)
67
Figure 6-22 Single Color 8-Bit Panel Timing (Format 2)
67
Figure 6-23 Single Color 8-Bit Panel A.C. Timing (Format 2)
68
Single Color 16-Bit Panel Timing
69
Figure 6-24 Single Color 16-Bit Panel Timing
69
Figure 6-25 Single Color 16-Bit Panel A.C. Timing
70
Dual Monochrome 8-Bit Panel Timing
71
Figure 6-26 Dual Monochrome 8-Bit Panel Timing
71
Figure 6-27 Dual Monochrome 8-Bit Panel A.C. Timing
72
Dual Color 8-Bit Panel Timing
73
Figure 6-28 Dual Color 8-Bit Panel Timing
73
Figure 6-29 Dual Color 8-Bit Panel A.C. Timing
74
Dual Color 16-Bit Panel Timing
75
Figure 6-30 Dual Color 16-Bit Panel Timing
75
Figure 6-31 Dual Color 16-Bit Panel A.C. Timing
76
TFT/D-TFD Panel Timing
77
Figure 6-32 TFT/D-TFD Panel Timing
77
Figure 6-33 TFT/D-TFD A.C. Timing
78
CRT Timing
80
Figure 6-34 CRT Timing
80
Figure 6-35 CRT A.C. Timing
81
TV Timing
82
TV Output Timing
82
Figure 6-36 NTSC Video Timing
82
Mediaplug Interface Timing
86
Clocks
87
Clock Overview
87
Clock Descriptions
88
Mclk
88
Lcd Pclk
88
Crt/Tv Pclk
88
Mediaplug Clock
88
Clock Selection
89
Clocks Vs. Functions
90
Registers
91
Initializing the S1D13806
91
Register Memory Select Bit
91
SDRAM Initialization Bit
91
Register Mapping
92
Register Set
93
Register Descriptions
95
Basic Registers
95
General IO Pins Registers
96
Configuration Readback Register
97
Clock Configuration Registers
97
Memory Configuration Registers
102
Panel Configuration Registers
103
LCD Display Mode Registers
109
CRT/TV Configuration Registers
113
CRT/TV Display Mode Registers
118
LCD Ink/Cursor Registers
121
CRT/TV Ink/Cursor Registers
125
Bitblt Configuration Registers
130
Look-Up Table Registers
138
Power Save Configuration Registers
139
Miscellaneous Registers
141
Common Display Mode Register
142
Mediaplug Registers Descriptions
143
Mediaplug Control Registers
143
Mediaplug Data Registers
147
Bitblt Data Registers Descriptions
147
Bit Blt Engine
148
Overview
148
Bitblt Operations
148
Display Buffer
149
Image Buffer
150
Ink Layer/Hardware Cursor Buffers
150
Dual Panel Buffer
150
Display Configuration
151
Display Mode Data Format
151
Image Manipulation
152
Look -U P Table Architecture
153
Monochrome Modes
153
Color Modes
154
Tv Considerations
156
NTSC/PAL Operation
156
Clock Source
156
Filters
157
Chrominance Filter (Reg[05Bh] Bit 5)
157
Luminance Filter (Reg[05Bh] Bit 4)
157
Anti-Flicker Filter (Reg[1Fch] Bits [2:1])
157
TV Output Levels
158
TV Image Display and Positioning
161
TV Cursor Operation
163
Ink Layer /Hardware Cursor Architecture
164
Ink Layer/Hardware Cursor Buffers
164
Ink/Cursor Data Format
165
Ink/Cursor Image Manipulation
166
Ink Image
166
Cursor Image
166
Swivel View
168
Concept
168
Register Programming
169
Physical Memory Requirement
171
Limitations
174
180° Swivelview
174
Register Programming
174
Limitations
175
270° Swivelview
175
Register Programming
175
Physical Memory Requirement
177
Limitations
177
Epson Independent Simultaneous Display (Eisd)
178
Registers
178
Display Mapping
178
Bandwidth Limitation
179
Media Plug Interface
180
Revision Code
180
How to Enable the Mediaplug Slave
180
Mediaplug Interface Pin Mapping
180
Clocking
181
Frame Rate Calculation
181
LCD Frame Rate Calculation
181
CRT Frame Rate Calculation
182
TV Frame Rate Calculation
183
Example Frame Rates
184
Frame Rates for 640 ¥ 480 with EISD Disabled
184
Frame Rates for 800 ¥ 600 with EISD Disabled
186
Frame Rates for 1024 ¥ 768 with EISD Disabled
187
Frame Rates for LCD and CRT (640 ¥ 480) with EISD Enabled
188
Frame Rates for LCD and CRT (800 ¥ 600) with EISD Enabled
189
Frame Rates for LCD and CRT (1024 ¥ 768) with EISD Enabled
190
Frame Rates for LCD and NTSC TV with EISD Enabled
191
Frame Rates for LCD and PAL TV with EISD Enabled
192
Power Save Mode
193
Overview
193
Power Save Status Bits
193
Power Save Mode Summary
194
Mechanical Data
195
Introduction
201
Initialization
202
Memory Models
206
Display Buffer Location
206
Memory Organization for 4 Bpp (16 Colors/16 Gray Shades)
206
Memory Organization for 8 Bpp (256 Colors/16 Gray Shades)
207
Memory Organization for 16 Bpp (65536 Colors/64 Gray Shades)
208
Look -U P Table (Lut)
209
Registers
209
Look-Up Table Organization
210
Color Modes
211
Gray Shade Modes
214
Virtual Displays
215
Virtual Display
215
Registers
216
Examples
217
Panning and Scrolling
219
Registers
220
Examples
222
Power Save Mode
224
Overview
224
Registers
224
Enabling Power Save Mode
224
Power Save Status Bits
225
Enabling Power Save Mode
226
Disabling Power Save Mode
226
Lcd Power Sequencing
227
Enabling the LCD Panel
228
Disabling the LCD Panel
228
Hardware Cursor /Ink Layer
229
Introduction
229
Registers
230
Initialization
236
Memory Considerations
236
Examples
237
Writing Cursor/Ink Layer Images
239
Hardware Cursor/Ink Layer Data Format
239
Cursor Image
240
Ink Layer Image
241
Cursor Movement
242
Move Cursor in Landscape Mode (no Rotation)
242
Move Cursor in Swivelview 90° Rotation
243
Move Cursor in Swivelview 180° Rotation
243
Move Cursor in Swivelview 270° Rotation
244
Swivel View
245
S1D13806 Swivelview
245
Registers
246
Limitations
247
Examples
248
Simultaneous Display Considerations
249
Bit Blt Engine
250
Registers
250
Bitblt Descriptions
257
Write Bitblt with ROP
258
Color Expand Bitblt
261
Color Expand Bitblt with Transparency
265
Solid Fill Bitblt
266
Move Bitblt in a Positive Direction with ROP
267
Move Bitblt in Negative Direction with ROP
269
Transparent Write Bitblt
271
Transparent Move Bitblt in Positive Direction
274
Pattern Fill Bitblt with ROP
275
Pattern Fill Bitblt with Transparency
277
Move Bitblt with Color Expansion
280
Transparent Move Bitblt with Color Expansion
281
Read Bitblt
282
S1D13806 Bitblt Synchronization
284
S1D13806 Bitblt Known Limitations
285
Crt/Tv Considerations
286
CRT Considerations
286
Generating CRT Timings with 1386CFG
286
DAC Output Level Selection
286
Examples
287
TV Considerations
287
NTSC Timings
287
PAL Timings
287
TV Filters
288
Examples
289
Simultaneous Display
289
Media Plug
290
Programming
290
Considerations
291
Identifying the S1D13806
292
1386Cfg
297
S1D13806 Supported Evaluation Platforms
297
Installation
297
Usage
298
1386CFG Configuration Tabs
298
General Tab
299
Clocks Tab
300
Panel Tab
302
CRT/TV Tab
304
Defaults Tab
305
Registers Tab
306
Wince Tab
307
Open File Dialog Box
308
Save in Dialog Box
309
Comments
310
1386Show
311
S1D13806 Supported Evaluation Platforms
311
Installation
311
Usage
312
Display Surfaces
313
1386SHOW Examples
314
Using 1386SHOW for Demonstration
314
Using 1386SHOW for Testing
316
Comments
317
Program Messages
318
1386Play
320
S1D13806 Supported Evaluation Platforms
320
Installation
321
Usage
321
Commands
322
1386PLAY Example
328
Scripting
329
Comments
329
Program Messages
330
1386Bmp
332
S1D13806 Supported Evaluation Platforms
332
Installation
332
Usage
333
Display Surfaces
334
1386BMP Examples
335
Comments
335
Program Messages
336
1386Swivel
338
S1D13806 Supported Evaluation Platforms
338
Installation
338
Usage
338
Example
339
Comments
339
1386Filt
340
S1D13806 Supported Evaluation Platforms
340
Installation
340
Usage
340
Filter Dialog Box
341
Filter Descriptions
342
Anti-Flicker Filter
342
Chrominance Filter
342
Luminance Filter
342
Introduction
348
Features
349
Installation and Configuration
350
Configuration DIP Switches
350
Configuration Jumpers
352
Cpu Host Interface
354
PCI Bus Support
354
On-Board PCI Configuration Registers
355
Read-Only Registers
355
Read/Write Registers
355
Utility Software
355
Non-PCI Host Interface Support
356
CPU Interface Pin Mapping
356
External CPU Host Connector Pin Mapping
357
Lcd Interface
359
LCD Connector Pin Mapping
359
Voltage Translation Buffers
360
Adjustable LCD Panel Positive Supply (VDDH )
360
Adjustable LCD Panel Negative Power Supply (VLCD )
360
LCD Power Sequencing
361
Crt/Tv Interface
362
CRT/TV Connectors Pin Mapping
362
DAC Output Level Select for CRT
362
Media Plug Interface ( for Winnov Videum ® Cam )
363
Mediaplug Interface Pin Mapping
363
Clock Synthesizer and Clock Options
364
Clock Programming
364
References
365
Parts List
366
Schematic Diagrams
369
Pcb Layout
377
Nterfacing to the Pc Card Us
382
Introduction
382
Interfacing to the PC Card Bus
383
The PC Card System Bus
383
Memory Access Cycles
384
S1D13806 Host Bus Interface
386
PC Card Host Bus Interface Pin Mapping
386
PC Card Host Bus Interface Signals
387
PC Card to S1D13806 Interface
388
Hardware Description
388
S1D13806 Hardware Configuration
390
Performance
390
Register/Memory Mapping
391
Inec Vr4102/Vr4111 M
392
Introduction
392
Interfacing to the VR4102/VR4111
393
The NEC VR4102/VR4111 System Bus
393
LCD Memory Access Cycles
394
S1D13806 Host Bus Interface
395
Host Bus Interface Pin Mapping
395
Host Bus Interface Signal Descriptions
396
VR4102/VR4111 to S1D13806 Interface
397
Hardware Description
397
S1D13806 Hardware Configuration
398
NEC VR4102/VR4111 Configuration
398
Register/Memory Mapping
399
Mmpc821 M
400
Introduction
400
Interfacing to the MPC821
401
The Mpc8Xx System Bus
401
MPC821 Bus Overview
401
Normal (Non-Burst) Bus Transactions
402
Burst Cycles
403
Memory Controller Module
404
User-Programmable Machine (UPM)
405
S1D13806 Host Bus Interface
406
Powerpc Host Bus Interface Pin Mapping
406
Powerpc Host Bus Interface Signals
407
MPC821 to S1D13806 Interface
408
Hardware Description
408
Hardware Connections
409
S1D13806 Hardware Configuration
411
Register/Memory Mapping
411
MPC821 Chip Select Configuration
412
Test Software
413
Introduction
414
Interfacing to the PR31500/PR31700
415
S1D13806 Host Bus Interface
416
PR31500/PR31700 Host Bus Interface Pin Mapping
416
PR31500/PR31700 Host Bus Interface Signals
417
Direct Connection to the Philips PR31500/PR31700
418
Hardware Description
418
S1D13806 Configuration
420
Memory Mapping and Aliasing
421
System Design Using the IT8368E PC Card Buffer
422
Hardware Description
422
IT8368E Configuration
423
S1D13806 Configuration
423
Introduction
424
Interfacing to the TX3912
425
S1D13806 Host Bus Interface
426
TX3912 Host Bus Interface Pin Mapping
426
TX3912 Host Bus Interface Signals
427
Direct Connection to the Toshiba TX3912
428
Hardware Description
428
S1D13806 Configuration
430
Memory Mapping and Aliasing
431
System Design Using the IT8368E PC Card Buffer
432
Hardware Description
432
IT8368E Configuration
433
S1D13806 Configuration
433
Introduction
434
Interfacing to the NEC VR4121
435
The NEC VR4121 System Bus
435
S1D13806 Host Bus Interface
437
Host Bus Interface Pin Mapping
437
Host Bus Interface Signal Descriptions
438
VR4121 to S1D13806 Interface
439
Hardware Description
439
S1D13806 Configuration
440
NEC VR4121 Configuration
440
Register/Memory Mapping
441
Introduction
442
Interfacing to the Strongarm SA-1110 Bus
443
The Strongarm SA-1110 System Bus
443
S1D13806 Host Bus Interface
446
Host Bus Interface Pin Mapping
446
Host Bus Interface Signal Descriptions
447
Strongarm SA-1110 to S1D13806 Interface
448
Hardware Description
448
S1D13806 Hardware Configuration
449
Performance
449
Strongarm SA-1110 Register Configuration
450
Register/Memory Mapping
451
Program Requirements
461

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Epson S1D13806 Series Technical Manual (471 pages)

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