Epson SED1354 Manuals

Manuals and User Guides for Epson SED1354. We have 1 Epson SED1354 manual available for free PDF download: Technical Manual

Epson SED1354 Technical Manual (328 pages)

Color Graphics LCD/CRT Controller

Brand: Epson | Category: Video Card | Size: 2 MB

Customer Support Information
3
Specification
5
System Block Diagram
8
Hardware Functional Specification
9
Table of Contents
11
List of Figures
17
Introduction
19
Scope
19
Overview Description
19
Features
20
Memory Interface
20
CPU Interface
20
Display Support
20
Display Modes
21
Clock Source
21
Miscellaneous
21
Typical System Implementation Diagrams
22
Figure 3-1: Typical System Diagram - SH-3 Bus, 1Mx16 FPM/EDO-DRAM
22
Figure 3-2: Typical System Diagram - MC68K Bus 1, 1Mx16 FPM/EDO-DRAM (16-Bit MC68000)
23
Figure 3-3: Typical System Diagram - MC68K Bus 2, 256Kx16 FPM/EDO-DRAM (32-Bit MC68030)
23
Figure 3-4: Typical System Diagram - Generic Bus, 1Mx16 FPM/EDO-DRAM
24
Block Description
25
Functional Block Diagram
25
Functional Block Descriptions
25
Host Interface
25
Memory Controller
25
Display FIFO
25
Figure 4-1: System Block Diagram Showing Datapaths
25
Look-Up Table
26
LCD Interface
26
Power Save
26
Pin out
27
Pinout Diagram
27
Figure 5-1: Pinout Diagram
27
Pin Description
28
Host Interface
28
Table 5-2: Host Interface Pin Descriptions
28
Memory Interface
30
Table 5-3: Memory Interface Pin Descriptions
30
LCD Interface
32
Clock Input
32
Table 5-1: LCD Interface Pin Descriptions
32
Table 5-2: Clock Input Pin Description
32
CRT and External RAMDAC Interface
33
Table 5-3: CRT and RAMDAC Interface Pin Descriptions
33
Miscellaneous
34
Power Supply
34
Table 5-4: Miscellaneous Pin Descriptions
34
Table 5-5: Power Supply Pin Descriptions
34
Summary of Configuration Options
35
Table 5-6: Summary of Power on / Reset Options
35
Multiple Function Pin Mapping
36
Table 5-7: Host Bus Interface Pin Mapping
36
Table 5-8: Memory Interface Pin Mapping
36
Table 5-9: LCD, CRT, RAMDAC Interface Pin Mapping
37
C. Characteristics
38
Table 6-1: Absolute Maximum Ratings
38
Table 6-2: Recommended Operating Conditions
38
Table 6-3: Input Specifications
38
Table 6-4: Output Specifications
39
C. Characteristics
40
CPU Interface Timing
40
Interface Timing
40
Figure 7-1: SH-3 Read Bus Timing
40
Table 7-1: SH-3 Read Bus Timing
41
Figure 7-2: SH-3 Write Bus Timing
42
Table 7-2: SH-3 Write Bus Timing
43
MC68K Bus 1 Interface Timing (E.g. MC68000)
44
Table 7-3: MC68000 Write Bus Timing
44
Figure 7-3: MC68000 Write Bus Timing
44
Table 7-4: MC68000 Read Bus Timing
45
Figure 7-4: MC68000 Read Bus Timing
45
MC68K Bus 2 Interface Timing (E.g. MC68030)
46
Table 7-5: MC68030 Write Bus Timing
46
Figure 7-5: MC68030 Write Bus Timing
46
Table 7-6: MC68030 Read Bus Timing
47
Figure 7-6: MC68030 Read Bus Timing
47
Generic MPU Interface Synchronous Timing
48
Table 7-7: Generic Read Bus Synchronous Timing
48
Figure 7-7: Generic Read Bus Synchronous Timing
48
Table 7-8: Generic Write Bus Synchronous Timing
49
Figure 7-8: Generic Write Bus Synchronous Timing
49
Generic MPU Interface Asynchronous Timing
50
Table 7-9: Generic Read Bus Asynchronous Timing
50
Figure 7-9: Generic Read Bus Asynchronous Timing
50
Table 7-10: Generic Write Bus Asynchronous Timing
51
Figure 7-10: Generic Write Bus Asynchronous Timing
51
Clock Input Requirements
52
Memory Interface Timing
52
EDO-DRAM Read Timing
52
Table 7-11: Clock Input Requirements
52
Figure 7-11: Clock Input Requirements
52
Figure 7-12: EDO-DRAM Read Timing
52
Table 7-12: EDO DRAM Read Timing
53
EDO-DRAM Write Timing
54
Figure 7-13: EDO-DRAM Write Timing
54
Table 7-13: EDO DRAM Write Timing
55
EDO-DRAM Read-Write Timing
56
Figure 7-14: EDO-DRAM Read-Write Timing
56
Table 7-14: EDO DRAM Read-Write Timing
57
EDO-DRAM cas before RAS Refresh Timing
58
Table 7-15: EDO-DRAM cas before RAS Refresh Timing
58
Figure 7-15: EDO-DRAM cas before RAS Refresh Timing
58
EDO-DRAM Self-Refresh Timing
59
Table 7-16: EDO-DRAM Self-Refresh Timing
59
Figure 7-16: EDO-DRAM Self-Refresh Timing
59
FPM-DRAM Read Timing
60
Figure 7-17: FPM-DRAM Read Timing
60
Table 7-17: FPM DRAM Read Timing
61
FPM-DRAM Write Timing
62
Figure 7-18: FPM-DRAM Write Timing
62
Table 7-18: FPM-DRAM Write Timing
63
FPM-DRAM Read-Write Timing
64
Figure 7-19: FPM-DRAM Read-Write Timing
64
Table 7-19: FPM-DRAM Read-Write Timing
65
FPM-DRAM CAS# before RAS# Refresh Timing
66
Table 7-20: FPM-DRAM CAS# before RAS# Refresh Timing
66
Figure 7-20: FPM-DRAM CAS# before RAS# Refresh Timing
66
FPM-DRAM Self-Refresh Timing
67
Table 7-21: FPM-DRAM CBR Self-Refresh Timing
67
Figure 7-21: FPM-DRAM CBR Self-Refresh Timing
67
Display Interface
68
Power on / Reset Timing
68
Table 7-22: LCD Panel Power on / Reset Timing
68
Figure 7-22: LCD Panel Power on / Reset Timing
68
Suspend Timing
69
Table 7-23: LCD Panel Suspend Timing
69
Figure 7-23: LCD Panel Suspend Timing
69
Single Monochrome 4-Bit Panel Timing
70
Figure 7-24: Single Monochrome 4-Bit Panel Timing
70
Table 7-24: Single Monochrome 4-Bit Panel A.C. Timing
71
Figure 7-25: Single Monochrome 4-Bit Panel A.C. Timing
71
Single Monochrome 8-Bit Panel Timing
72
Figure 7-26: Single Monochrome 8-Bit Panel Timing
72
Table 7-25: Single Monochrome 8-Bit Panel A.C. Timing
73
Figure 7-27: Single Monochrome 8-Bit Panel A.C. Timing
73
Single Color 4-Bit Panel Timing
74
Figure 7-28: Single Color 4-Bit Panel Timing
74
Table 7-26: Single Color 4-Bit Panel A.C. Timing
75
Figure 7-29: Single Color 4-Bit Panel A.C. Timing
75
Single Color 8-Bit Panel Timing (Format 1)
76
Figure 7-30: Single Color 8-Bit Panel Timing (Format 1)
76
Table 7-27: Single Color 8-Bit Panel A.C. Timing (Format 1)
77
Figure 7-31: Single Color 8-Bit Panel A.C. Timing (Format 1)
77
Single Color 8-Bit Panel Timing (Format 2)
78
Figure 7-32: Single Color 8-Bit Panel Timing (Format 2)
78
Table 7-28: Single Color 8-Bit Panel A.C. Timing (Format 2)
79
Figure 7-33: Single Color 8-Bit Panel A.C. Timing (Format 2)
79
Single Color 16-Bit Panel Timing
80
Figure 7-34: Single Color 16-Bit Panel Timing
80
Table 7-29: Single Color 16-Bit Panel A.C. Timing
81
Figure 7-35: Single Color 16-Bit Panel A.C. Timing
81
Dual Monochrome 8-Bit Panel Timing
82
Figure 7-36: Dual Monochrome 8-Bit Panel Timing
82
Table 7-30: Dual Monochrome 8-Bit Panel A.C. Timing
83
Figure 7-37: Dual Monochrome 8-Bit Panel A.C. Timing
83
Dual Color 8-Bit Panel Timing
84
Figure 7-38: Dual Color 8-Bit Panel Timing
84
Table 7-31: Dual Color 8-Bit Panel A.C. Timing
85
Figure 7-39: Dual Color 8-Bit Panel A.C. Timing
85
Dual Color 16-Bit Panel Timing
86
Figure 7-40: Dual Color 16-Bit Panel Timing
86
Table 7-32: Dual Color 16-Bit Panel A.C. Timing
87
Figure 7-41: Dual Color 16-Bit Panel A.C. Timing
87
16-Bit TFT Panel Timing
88
Figure 7-42: 16-Bit TFT Panel Timing
88
Figure 7-43: TFT A.C. Timing
89
Table 7-33: TFT A.C. Timing
90
CRT Timing
91
Figure 7-44: CRT Timing
91
Figure 7-45: CRT A.C. Timing
92
Table 7-34: CRT A.C. Timing
93
External RAMDAC Read / Write Timing
94
Table 7-35: Generic Bus RAMDAC Read / Write Timing
94
Figure 7-46: Generic Bus RAMDAC Read / Write Timing
94
Registers
95
Register Mapping
95
Register Descriptions
95
Revision Code Register
95
Table 8-1: SED1354 Addressing
95
Memory Configuration Registers
96
Table 8-2: DRAM Refresh Rate Selection
96
Panel/Monitor Configuration Registers
97
Table 8-3: Panel Data Width Selection
97
Table 8-4: FPLINE Polarity Selection
99
Table 8-5: FPFRAME Polarity Selection
101
Display Configuration Registers
102
Table 8-6: Simultaneous Display Option Selection
102
Table 8-7: Number of Bits-Per-Pixel Selection
103
Clock Configuration Register
106
Table 8-8: Pixel Panning Selection
106
Table 8-9: PCLK Divide Selection
106
Power Save Configuration Registers
107
Miscellaneous Registers
107
Table 8-10: Suspend Refresh Selection
107
Table 8-11: Minimum Memory Timing Selection
112
Table 8-12: RAS-To-CAS Delay Timing Select
113
Table 8-13: RAS Precharge Timing Select
113
Table 8-14: Optimal NRC, NRP, and NRCD Values at Maximum MCLK Frequency
113
Look-Up Table Registers
114
Table 8-15: RGB Index Selection
114
External RAMDAC Control Registers
116
Display Buffer
118
Table 9-1: SED1354 Addressing
118
Figure 9-1: Display Buffer Addressing
118
Image Buffer
119
Half Frame Buffer
119
Display Configuration
120
Display Mode Data Format
120
Figure 10-1: 1/2/4/8 Bit-Per-Pixel Format Memory Organization
120
Figure 10-2: 15/16 Bit-Per-Pixel Format Memory Organization
121
Image Manipulation
122
Figure 10-3: Image Manipulation
122
Frame Rate Calculation
123
Table 11-1: Maximum Frame Rates
123
Look-Up Table Architecture
126
Gray Shade Display Modes
126
Table 12-1: Look-Up Table Configurations
126
Figure 12-1: 1 Bit-Per-Pixel - 2-Level Gray-Shade Mode Look-Up Table Architecture
126
Figure 12-2: 2 Bit-Per-Pixel - 4-Level Gray-Shade Mode Look-Up Table Architecture
127
Figure 12-3: 4 Bit-Per-Pixel - 16-Level Gray-Shade Mode Look-Up Table Architecture
127
Color Display Modes
128
Figure 12-4: 1 Bit-Per-Pixel - 2-Level Color Look-Up Table Architecture
128
Figure 12-5: 2 Bit-Per-Pixel - 4-Level Color Mode Look-Up Table Architecture
129
Figure 12-6: 4 Bit-Per-Pixel - 16-Level Color Mode Look-Up Table Architecture
130
Figure 12-7: 8 Bit-Per-Pixel - 256-Level Color Mode Look-Up Table Architecture
131
Power Save Modes
132
Hardware Suspend
132
Software Suspend
132
Power Save Mode Function Summary
133
Pin States in Power Save Modes
133
Table 13-1: Power Save Mode Function Summary
133
Table 13-2: Pin States in Power Save Modes
133
Mechanical Data
134
Figure 14-1: Mechanical Drawing QFP15
134
Programming Notes and Examples
135
Introduction
141
Initializing the SED1354
142
Display Buffer
146
Display Buffer Location
146
Display Buffer Organization
146
Memory Organization for One Bit-Per-Pixel (2 Colors/Gray Shades)
146
Memory Organization for Two Bit-Per-Pixel (4 Colors/Gray Shades)
146
Memory Organization for Four Bit-Per-Pixel (16 Colors/Gray Shades)
147
Memory Organization for Eight Bit-Per-Pixel (256 Colors)
147
Memory Organization for 15 Bit-Per-Pixel (32768 Colors)
148
Memory Organization for 16 Bit-Per-Pixel (65536 Colors)
148
Look-Up Table (LUT)
149
Look-Up Table Registers
149
Look-Up Table Organization
151
Advanced Techniques
157
Virtual Display
157
Registers
158
Examples
158
Panning and Scrolling
159
Registers
160
Examples
161
Split Screen
162
Registers
162
Examples
163
LCD Power Sequencing and Power Save Modes
164
Introduction to LCD Power Sequencing
164
Introduction to Power Save Modes
164
Registers
164
Software Suspend
165
LCD Enable / Disable
165
Hardware Suspend
166
CRT Considerations
167
Introduction
167
CRT Only
167
Simultaneous Display
168
Identifying the SED1354
172
Hardware Abstraction Layer (HAL)
173
Introduction
173
API for 1354HAL
173
Initialization
173
Screen Manipulation
175
Color Manipulation
181
Drawing
184
Register Manipulation
186
Miscellaneous
186
Sample Code
188
Introduction
188
Sample Code Using 1354HAL API
188
Sample Code Without Using 1354HAL API
189
Appendix A Supported Panel Values
196
Supported Panel Values
196
1354Cfg.exe
207
Program Requirements
208
Installation
208
Usage
208
Script Mode
209
Interactive Mode
210
1354CFG Menu Bar
210
Viewing 1354CFG Menu Contents
210
Making 1354CFG Menu Selections
211
Files Menu
212
View Menu
213
Device Menu
215
Panel
215
Crt
215
Advanced Memory
215
Power Management
215
Power Management
222
Lookup Table (LUT)
224
Setup
226
Help Menu
227
Comments
228
Sample Program Messages
228
Installation
231
Program Messages
232
Installation and Configuration
268
CPU / BUS Interface Connector Pinouts
270
Host Bus Interface Pin Mapping
272
Technical Description
273
Non-ISA Bus Support
273
Adjustable LCD Panel Negative Power Supply
276
Adjustable LCD Panel Positive Power Supply
276
Cpu/Bus Interface Header Strips
276
Schematic Notes
276
Parts List
277
Schematic Diagrams
279
Introduction
291
Features
292
SED1354 Color Graphics LCD Controller
292
Display Buffer
292
LCD Display Support
293
LCD Interface Pin Mapping
294
CRT Support
295
Adjustable LCD BIAS Power Supply
295
D9000 Specifics
296
Interface Signals
296
Connector Pinout for Channel A10 and A11
297
Bus Interface Timing
301
Memory Address (CS#, M/R#) Decode
301
Makefpga File
301
Board Dimensions
301
Support Documentation Notes
301
Parts List
302
Schematic Diagrams
303
PCB Layout
307
Component Placement
307
Perspective View
308
Power Consumption
309
Introduction
317
General Description
317
SED1354 Implementation
318
Hardware Description
318
Configuration
319
Sed1354
319
It8368E
319
Software
320
Technical Support
320
Epson LCD Controllers (SED1354)
320
Philips Processor PR31500 / PR31700
320
Ite It8368E
320
Introduction
325
General Description
325
SED1354 Configuration
326
Hardware Description
326
Software
328
Technical Support
328
Epson LCD Controllers (SED1354)
328
NEC Electronics Inc
328

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