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Epson S1D13806 Series Technical Manual

Embedded dram graphics controller

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MF1430-01

Embedded DRAM Graphics Controller

S1D13806 Series

Technical Manual

Table of Contents

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Summary of Contents for Epson S1D13806 Series

Page 1 MF1430-01 Embedded DRAM Graphics Controller S1D13806 Series Technical Manual...
Page 2 Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products.
Page 3: Evaluation Board
New configuration of product number Starting April 1, 2001, the configuration of product number descriptions will be changed as listed below. To order from April 1, 2001 please use these product numbers. For further information, please contact Epson sales representative. Devices 13706...
Page 4: Hardware Functional Specification
S1D13806 Series Technical Manual HARDWARE FUNCTIONAL SPECIFICATION PROGRAMMING NOTES AND EXAMPLES UTILITIES S5U13806B00C REV. 1.0 EVALUATION BOARD USER’S MANUAL APPLICATION NOTES POWER CONSUMPTION ® WINDOWS CE DISPLAY DRIVER...
Page 6: Table Of Contents
Dual Color 8-Bit Panel Timing.................. 1-61 6.4.9 Dual Color 16-Bit Panel Timing................1-63 6.4.10 TFT/D-TFD Panel Timing..................1-65 6.4.11 CRT Timing ......................1-68 TV Timing..........................1-70 6.5.1 TV Output Timing ..................... 1-70 MediaPlug Interface Timing ...................... 1-74 EPSON S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION...
Page 7 12.1 Monochrome Modes ....................... 1-141 12.2 Color Modes ........................... 1-142 13 TV C ......................1-144 ONSIDERATIONS 13.1 NTSC/PAL Operation ......................1-144 13.2 Clock Source .......................... 1-144 13.3 Filters ............................1-145 13.3.1 Chrominance Filter (REG[05Bh] bit 5) ..............1-145 EPSON 1-ii S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION...
Page 8 18.2.8 Frame Rates for LCD and PAL TV with EISD Enabled.......... 1-180 19 P ......................1-181 OWER 19.1 Overview ..........................1-181 19.2 Power Save Status Bits......................1-181 19.3 Power Save Mode Summary ....................1-182 20 M ......................1-183 ECHANICAL EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-iii SPECIFICATION...
Page 9 Figure 6-32 TFT/D-TFD Panel Timing....................1-65 Figure 6-33 TFT/D-TFD A.C. Timing ..................... 1-66 Figure 6-34 CRT Timing ........................1-68 Figure 6-35 CRT A.C. Timing ........................ 1-69 Figure 6-36 NTSC Video Timing ......................1-70 EPSON 1-iv S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION...
Page 10 Table 6-9 Motorola MC68K Bus 1 Interface Timing ................1-34 Table 6-10 Motorola MC68K Bus 2 Interface Timing ................1-36 Table 6-11 Motorola PowerPC Interface Timing .................. 1-38 Table 6-12 PC Card Timing........................1-40 EPSON S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION...
Page 11 BitBLT FIFO Words Available ..................1-118 Table 8-30 BitBLT ROP Code/Color Expansion Function Selection ..........1-120 Table 8-31 BitBLT Operation Selection....................1-121 Table 8-32 BitBLT Source Start Address Selection ................1-122 Table 8-33 LUT Mode Selection ......................1-126 EPSON 1-vi S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION...
Page 12 Table 18-7 Frame Rates for LCD and NTSC TV with EISD Enabled..........1-179 Table 18-8 Frame Rates for LCD and PAL TV with EISD Enabled............ 1-180 Table 19-1 Power Save Mode Summary.................... 1-182 EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-vii SPECIFICATION...
Page 13: Introduction
The S1D13806 supports multiple CPUs, all LCD panel types, CRT, TV, and additionally provides a number of differentiating features. EPSON Independent Simultaneous Display technology allows the user to configure two different images on two different displays, while the SwivelView™, Hard- ware Cursor, Ink Layer, and BitBLT features offer substantial performance benefits.
Page 14: Features
SwivelView™: 90°, 180°, 270° hardware rotation of display MPU bus interface with programmable READY. image. NEC MIPS VR41xx. EPSON Independent Simultaneous Display (EISD): displays PC Card (PCMCIA). independent images on different displays (CRT or TV and pas- Philips MIPS PR31500/PR31700.
Page 15: System Implementation
D[15:0] DB[15:0] FPLINE FPLINE DRDY WE1# WE1# S1D13806 RD/WR# GPIOx RD/WR# GREEN WE0# Composite Video WE0# RDY# WAIT# Composite CKIO BUSCLK RESET# RESET# IREF IREF Figure 3-2 Typical System Diagram (Hitachi SH-4 Bus) EPSON S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 16: Typical System Implementation Diagrams
FPLINE FPLINE DRDY S1D13806 LDS# UDS# WE1# GPIOx R/W# RD/WR# Luminance DTACK# BLUE WAIT# Chrominance S-Video BCLK BUSCLK RESET# IREF RESET# IREF Figure 3-4 Typical System Diagram (MC68K Bus 1, Motorola 16-Bit 68000) EPSON S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 17: Figure 3-5 Typical System Diagram (Mc68K Bus 2, Motorola 32-Bit 68030)
D[0:15] DB[15:0] FPLINE FPLINE DRDY WE1# S1D13806 RD/WR# GPIOx RD/WR# TSIZ0 RED,GREEN,BLUE TSIZ1 WE0# Composite Video WAIT# Composite CLKOUT BUSCLK RESET# IREF RESET# IREF Figure 3-6 Typical System Diagram (Motorola Power PC Bus) EPSON S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 18: Figure 3-7 Typical System Diagram (Nec Mips Vr41Xx Bus)
A[20:0] AB[20:0] DRDY D[15:0] DB[15:0] S1D13806 WE0# CE2# WE1# GPIOx CE1# RD/WR# Luminance WAIT# BLUE WAIT# Chrominance S-Video TV BCLK BUSCLK RESET# IREF RESET# IREF Figure 3-8 Typical System Diagram (PC Card Bus) EPSON S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 19: Figure 3-9 Typical System Diagram (Philips Mips Pr31500/Pr31700 Bus)
AB19 S1D13806 CARDIORD* AB18 CARDIOWR* AB17 GPIOx CARDxCSH* WE1# RED,GREEN,BLUE Composite Video CARDxCSL* RD/WR# Composite WE0# CARDxWAIT* WAIT# DCLKOUT BUSCLK IREF PON* IREF RESET# Figure 3-10 Typical System Diagram (Toshiba MIPS TX39xx Bus) EPSON S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 20: Pins
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Figure 4-1 Pinout Diagram 144-pin QFP20 surface mount package EPSON S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 21: Pin Description
(1 = 2/-2mA, 2 = 6/-6mA @ 3.3V) Tri-state CMOS output driver with pull down resistor (typical value of 100ΚΩ at 3.3V), x denotes driver TSxD type (1 = 2/-2mA, 2 = 6/-6mA @ 3.3V) EPSON S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 22: Host Interface
• For all other busses, this pin inputs the system address bit 20 (A20). See Table 4-9, “CPU Interface Pin Mapping,” on page 18 for summary. See the respective AC Timing diagram for detailed functionality. EPSON 1-10 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 23 • For PC Card (PCMCIA) Bus, this pin is connected to the input clock (CLKI, pin 69). See Table 4-9, “CPU Interface Pin Mapping,” on page 18 for summary. See the respective AC Timing diagram for detailed functionality. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-11 SPECIFICATION (X28B-A-001-03)
Page 24 • For PC Card (PCMCIA) Bus, this pin inputs the output enable signal (-OE). See Table 4-9, “CPU Interface Pin Mapping,” on page 18 for summary. See the respective AC Timing diagram for detailed functionality. EPSON 1-12 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 25 See the respective AC Timing diagram for detailed functionality. Note: When WAIT# is always driven, WAIT# is in its inactive state at RESET#. CONF[3:0] determines whether WAIT# is active high or low. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-13 SPECIFICATION (X28B-A-001-03)
Page 26: Lcd Interface
MediaPlug VMPCLKN pin. Note: The RESET# states of VMP[5:2] are 0 if VMP is enabled, otherwise Hi-Z. Note: When the MediaPlug interface is enabled, GPIO12 is configured as the MediaPlug output pin VMPEPWR. EPSON 1-14 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 27: Crt Interface
MediaPlug output pin VMPEPWR. 135-137, 57, GPIO[11:0] 61, 63, 65, C/TS2 Hi-Z Bi-directional GPIO pin. 67-71 Note: The RESET# state of GPIO12 is 1 if MediaPlug is enabled, otherwise Hi-Z. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-15 SPECIFICATION (X28B-A-001-03)
Page 28: Configuration
88, 99, 108, — 121, 144 for DAC (DAC V AVSS 111, 118 — for embedded SDRAM (SDRAM V DVSS 58, 143 — N.C. — — — This pin must not be connected. EPSON 1-16 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 29: Summary Of Configuration Options
WAIT# is tristated when the chip is not accessed by the host Configures GPIO12 as MediaPlug output pin Configure GPIO12 for normal use and disables MediaPlug func- CONF7 VMPEPWR and enables MediaPlug functionality. tionality. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-17 SPECIFICATION (X28B-A-001-03)
Page 30: Multiple Function Pin Mapping
RESET# RESET# RESET# PON* RESET RESET Note: All GPIO pins default to input on reset and unless programmed otherwise, should be connected to ei- ther V or IO V if not used. EPSON 1-18 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 31: Table 4-10 Lcd Interface Pin Mapping
0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 FPDAT23 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-19 SPECIFICATION (X28B-A-001-03)
Page 32: Crt/Tv Interface
To CRT/TV 150Ω 150Ω 150Ω DAC V DAC V DAC V Figure 4-2 External Circuitry for CRT Interface Note: Example implementation only, individual characteristics of components may affect actual IREF cur- rent. EPSON 1-20 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 33: Table 5-1 Absolute Maximum Ratings
IO V Supply Voltage = 0 V Core V Supply Voltage = 0 V DAC V Supply Voltage = 0 V SDRAM V Supply Voltage = 0 V Input Voltage °C Operating Temperature EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-21 SPECIFICATION (X28B-A-001-03)
Page 34: Table 5-3 Electrical Characteristics For Vdd = 3.3V Typical
LVTTL Schmitt Hysteresis Voltage LVTTL Schmitt Pull-Down Resistance Type 1 kΩ Type 2 kΩ Pull-Up Resistance = 0V Type 1 kΩ Type 2 kΩ Input Pin Capacitance Output Pin Capacitance Bi-Directional Pin Capacitance EPSON 1-22 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 35: C. Characteristics
Input Clock Fall Time (10% - 90%) Input Clock Rise Time (10% - 90%) Note: The internal memory clock (MCLK) is restricted to a maximum of 50MHz and a minimum of 5MHz. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-23 SPECIFICATION (X28B-A-001-03)
Page 36: Internal Clocks
The TV pixel clock for NTSC output is fixed at 14.318MHz. The TV pixel clock for PAL output is fixed at 17.734MHz. Note: For further information on the internal clocks, refer to Section 7, “Clocks” on page 75. EPSON 1-24 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 37: Cpu Interface Timing
D[15:0](write) D[15:0](read) Figure 6-2 Generic Interface Timing Note: The above timing diagram is not applicable if CONF5 = 1 (BUSCLK divided by 2). Note: WAIT# is always driven when CONF6 = 1. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-25 SPECIFICATION (X28B-A-001-03)
Page 38: Table 6-5 Generic Interface Timing
WE1# = 0 (write cycle) D[15:0] hold (write cycle) Falling edge RD0#, RD1# to D[15:0] driven (read cycle) D[15:0] setup to rising edge WAIT# (read cycle) Rising edge of RD0#, RD1# to D[15:0] tri-state (read cycle) EPSON 1-26 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 39: Hitachi Sh-4 Interface Timing
Note: The SH-4 Wait State Control Register for the area in which the S1D13806 resides must be set to a non-zero value. The SH-4 read-to-write cycle transition must be set to a non-zero value (with refer- ence to BUSCLK). Note: RDY# is always driven when CONF6 = 1. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-27 SPECIFICATION (X28B-A-001-03)
Page 40: Table 6-6 Hitachi Sh-4 Interface Timing
DB[15:0] valid to RDY# falling edge (read cycle) Rising edge RD# to DB[15:0] tri-state (read cycle) CSn# high setup to CKIO Falling edge CKIO to RDY# tri-state Note: 1. Two software WAIT states are required. EPSON 1-28 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 41: Hitachi Sh-3 Interface Timing
Note: The above timing diagram is not applicable if CONF5 = 1 (BUSCLK divided by 2). Note: The SH-3 Wait State Control Register for the area in which the S1D13806 resides must be set to a non-zero value. Note: WAIT# is always driven when CONF6 = 1. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-29 SPECIFICATION (X28B-A-001-03)
Page 42: Table 6-7 Hitachi Sh-3 Interface Timing
DB[15:0] valid to WAIT# rising edge (read cycle) Rising edge RD# to DB[15:0] tri-state (read cycle) CSn# high setup to CKIO Note: 1. Two software WAIT states are required when f is greater than 33MHz. CKIO EPSON 1-30 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 43: Mips/Isa Interface Timing (E.g. Nec Vr41Xx)
SD[15:0](write) SD[15:0](read) Figure 6-5 MIPS/ISA Interface Timing Note: The above timing diagram is not applicable if CONF5 = 1 (BUSCLK divided by 2). Note: IOCHRDY is always driven when CONF6 = 1. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-31 SPECIFICATION (X28B-A-001-03)
Page 44: Table 6-8 Mips/Isa Interface Timing
MEMW# = 0 (write cycle) SD[15:0] hold (write cycle) Falling edge MEMR# toSD[15:0] driven (read cycle) SD[15:0] setup to rising edge IOCHRDY# (read cycle) Rising edge of MEMR# toSD[15:0] tri-state (read cycle) EPSON 1-32 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 45: Motorola Mc68K Bus 1 Interface Timing (E.g. Mc68000)
Figure 6-6 Motorola MC68K Bus 1 Interface Timing Note: The above timing diagram is not applicable if CONF5 = 1 (BUSCLK divided by 2). Note: DTACK# is always driven when CONF6 = 1. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-33 SPECIFICATION (X28B-A-001-03)
Page 46: Table 6-9 Motorola Mc68K Bus 1 Interface Timing
Falling edge of UDS# = 0 or LDS# = 0 to DB driven (read cycle) D[15:0] valid to DTACK# falling edge (read cycle) UDS# and LDS# high to D[15:0] invalid/high impedance (read cycle) AS# high setup to CLK EPSON 1-34 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 47: Motorola Mc68K Bus 2 Interface Timing (E.g. Mc68030)
Figure 6-7 Motorola MC68K Bus 2 Interface Timing Note: The above timing diagram is not applicable if CONF5 = 1 (BUSCLK divided by 2). Note: DSACK1# is always driven when CONF6 = 1. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-35 SPECIFICATION (X28B-A-001-03)
Page 48: Table 6-10 Motorola Mc68K Bus 2 Interface Timing
Falling edge of DS# = 0 to DB driven (read cycle) D[31:16] valid to DSACK1# falling edge (read cycle) DS# high to D[31:16] invalid/high impedance (read cycle) AS# high setup to CLK EPSON 1-36 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 49: Motorola Powerpc Interface Timing (E.g. Mpc8Xx, Mc68040, Coldfire)
D[0:15](read) Figure 6-8 Motorola PowerPC Interface Timing Note: The above timing diagram is not applicable if CONF5 = 1 (BUSCLK divided by 2). Note: TA# is always driven when CONF6 = 1. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-37 SPECIFICATION (X28B-A-001-03)
Page 50: Table 6-11 Motorola Powerpc Interface Timing
DB[15:0] hold (write cycle) CLKOUT to DB driven (read cycle) DB[15:0] valid to TA# falling edge (read cycle) CLKOUT to DB[15:0] tri-state (read cycle) Note: Output pin loading on DB[15:0], TA#, BI# is 10pF. EPSON 1-38 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 51: Pc Card Timing (E.g. Strongarm)
6.2.8 PC Card Timing (e.g. StrongARM) A[20:0] M/R# -CE[1:0] -WAIT D[15:0](write) D[15:0](read) Figure 6-9 PC Card Timing Note: The above timing diagram is not applicable if CONF5 = 1 (BUSCLK divided by 2). EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-39 SPECIFICATION (X28B-A-001-03)
Page 52: Table 6-12 Pc Card Timing
D[15:0] setup to third CLK where -CE = 0 and -WE = 0 (write cycle) D[15:0] hold (write cycle) Falling edge -OE to D[15:0] driven (read cycle) D[15:0] setup to rising edge -WAIT (read cycle) Rising edge of -OE to D[15:0] tri-state (read cycle) EPSON 1-40 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 53: Philips Interface Timing (E.g. Pr31500/Pr31700)
6.2.9 Philips Interface Timing (e.g. PR31500/PR31700) DCLKOUT DCLKOUT ADDR[12:0] /CARDREG /CARDxCSH /CARDxCSL /CARDIORD /CARDIOWR /WE /RD /CARDxWAIT D[31:16](write) D[31:16](read) Figure 6-10 Philips Interface Timing Note: /CARDxWAIT is always driven when CONF6 = 1. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-41 SPECIFICATION (X28B-A-001-03)
Page 54 D[31:16] setup to rising edge /CARDxWAIT (read cycle) Command invalid to D[31:16] tri-state (read cycle) Note: If BUSCLK exceeds 37.5MHz, it must be divided by 2 using CONF5 (see Table 4-8, “Summary of Power-On/Reset Options,” on page 17). EPSON 1-42 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 55: Toshiba Interface Timing (E.g. Tx39Xx)
6.2.10 Toshiba Interface Timing (e.g. TX39xx) DCLKOUT DCLKOUT ADDR[12:0] CARDREG* CARDxCSH* CARDxCSL* CARDIORD* CARDIOWR* WE* RD* CARDxWAIT* D[31:16](write) D[31:16](read) Figure 6-11 Toshiba Interface Timing Note: CARDxWAIT* is always driven when CONF6 = 1. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-43 SPECIFICATION (X28B-A-001-03)
Page 56 D[31:16] setup to rising edge CARDxWAIT* (read cycle) Command invalid to D[31:16] tri-state (read cycle) Note: If BUSCLK exceeds 37.5MHz, it must be divided by 2 using CONF5 (see Table 4-8, “Summary of Power-On/Reset Options,” on page 17). EPSON 1-44 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 57: Power Sequencing
LCD Enable Bit high to FPFRAME, FPLINE, FPLINE FPSHIFT, FPDATA, DRDY active Note: Where T is the period of FPLINE. FPLINE Note: The above timing assumes REG[1F0h] bit 4 is set to 1. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-45 SPECIFICATION (X28B-A-001-03)
Page 58: Power Save Status
1. t2 = The maximum value for t2 is based on the SDRAM Refresh Rate (REG[021h] bits 2:0) as follows. Table 6-17 SDRAM Refresh Period Selection SDRAM Refresh Period REG[021h] bits 2:0 (MCLKs) EPSON 1-46 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 59: Display Interface
= (REG[03Ah] bits [5:0]) + 1 = ((REG[032h] bits [6:0]) + 1) × 8Ts HDP = Horizontal Display Period = ((REG[034h] bits [4:0]) + 1) × 8Ts HNDP = Horizontal Non-Display Period EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-47 SPECIFICATION (X28B-A-001-03)
Page 60: Figure 6-15 Single Monochrome 4-Bit Panel A.c. Timing
= [((REG[034h] bits [4:0]) + 1) × 8 - 14] for 16 bpp color depth 7. t10 = 17 for 4 bpp or 8 bpp color depth = 16 for 16 bpp color depth EPSON 1-48 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 61: Single Monochrome 8-Bit Panel Timing
= Vertical Non-Display Period = (REG[03Ah] bits [5:0]) + 1 = ((REG[032h] bits [6:0]) + 1) × 8Ts = Horizontal Display Period = ((REG[034h] bits [4:0]) + 1) × 8Ts HNDP = Horizontal Non-Display Period EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-49 SPECIFICATION (X28B-A-001-03)
Page 62: Figure 6-17 Single Monochrome 8-Bit Panel A.c. Timing
= [((REG[034h] bits [4:0]) + 1) × 8 - 12] for 16 bpp color depth 7. t10 = 17 for 4 bpp or 8 bpp color depth = 16 for 16 bpp color depth EPSON 1-50 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 63: Single Color 4-Bit Panel Timing
= Vertical Non-Display Period = (REG[03Ah] bits [5:0]) + 1 = ((REG[032h] bits [6:0]) + 1) × 8Ts = Horizontal Display Period = ((REG[034h] bits [4:0]) + 1) × 8Ts HNDP = Horizontal Non-Display Period EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-51 SPECIFICATION (X28B-A-001-03)
Page 64: Figure 6-19 Single Color 4-Bit Panel A.c. Timing
= [((REG[034h] bits [4:0]) + 1) × 8 - 16.5] for 16 bpp color depth 7. t10 = 18 for 4 bpp or 8 bpp color depth = 17 for 16 bpp color depth EPSON 1-52 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 65: Single Color 8-Bit Panel Timing (Format 1)
= Vertical Non-Display Period = (REG[03Ah] bits [5:0]) + 1 = ((REG[032h] bits [6:0]) + 1) × 8Ts = Horizontal Display Period = ((REG[034h] bits [4:0]) + 1) × 8Ts HNDP = Horizontal Non-Display Period EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-53 SPECIFICATION (X28B-A-001-03)
Page 66: Figure 6-21 Single Color 8-Bit Panel A.c. Timing (Format 1)
= [((REG[034h] bits [4:0]) + 1) × 8 - 14] for 16 bpp color depth 8. t9 = 17 for 4 bpp or 8 bpp color depth = 16 for 16 bpp color depth EPSON 1-54 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 67: Single Color 8-Bit Panel Timing (Format 2)
= Vertical Non-Display Period = (REG[03Ah] bits [5:0]) + 1 = ((REG[032h] bits [6:0]) + 1) × 8Ts = Horizontal Display Period = ((REG[034h] bits [4:0]) + 1) × 8Ts HNDP = Horizontal Non-Display Period EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-55 SPECIFICATION (X28B-A-001-03)
Page 68: Figure 6-23 Single Color 8-Bit Panel A.c. Timing (Format 2)
= [((REG[034h] bits [4:0]) + 1) × 8 - 15] for 16 bpp color depth 7. t10 = 17 for 4 bpp or 8 bpp color depth = 16 for 16 bpp color depth EPSON 1-56 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 69: Single Color 16-Bit Panel Timing
= Vertical Non-Display Period = (REG[03Ah] bits [5:0]) + 1 = ((REG[032h] bits [6:0]) + 1) × 8Ts = Horizontal Display Period = ((REG[034h] bits [4:0]) + 1) × 8Ts HNDP = Horizontal Non-Display Period EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-57 SPECIFICATION (X28B-A-001-03)
Page 70: Figure 6-25 Single Color 16-Bit Panel A.c. Timing
= [((REG[034h] bits [4:0]) + 1) × 8 - 14] for 16 bpp color depth 7. t10 = 17 for 4 bpp or 8 bpp color depth = 16 for 16 bpp color depth EPSON 1-58 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 71: Dual Monochrome 8-Bit Panel Timing
= Vertical Non-Display Period = (REG[03Ah] bits [5:0]) + 1 = ((REG[032h] bits [6:0]) + 1) × 8Ts = Horizontal Display Period = ((REG[034h] bits [4:0]) + 1) × 8Ts HNDP = Horizontal Non-Display Period EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-59 SPECIFICATION (X28B-A-001-03)
Page 72: Figure 6-27 Dual Monochrome 8-Bit Panel A.c. Timing
= [((REG[034h] bits [4:0]) + 1) × 8 - 6] for 16 bpp color depth 7. t10 = 9 for 4 bpp or 8 bpp color depth = 8 for 16 bpp color depth EPSON 1-60 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 73: Dual Color 8-Bit Panel Timing
= Vertical Non-Display Period = (REG[03Ah] bits [5:0]) + 1 = ((REG[032h] bits [6:0]) + 1) × 8Ts = Horizontal Display Period = ((REG[034h] bits [4:0]) + 1) × 8Ts HNDP = Horizontal Non-Display Period EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-61 SPECIFICATION (X28B-A-001-03)
Page 74: Figure 6-29 Dual Color 8-Bit Panel A.c. Timing
= [((REG[034h] bits [4:0]) + 1) × 8 - 6.5] for 16 bpp color depth 7. t10 = 10 for 4 bpp or 8 bpp color depth = 9 for 16 bpp color depth EPSON 1-62 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 75: Dual Color 16-Bit Panel Timing
= Vertical Non-Display Period = (REG[03Ah] bits [5:0]) + 1 = ((REG[032h] bits [6:0]) + 1) × 8Ts = Horizontal Display Period = ((REG[034h] bits [4:0]) + 1) × 8Ts HNDP = Horizontal Non-Display Period EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-63 SPECIFICATION (X28B-A-001-03)
Page 76: Figure 6-31 Dual Color 16-Bit Panel A.c. Timing
= [((REG[034h] bits [4:0]) + 1) × 8 - 7] for 16 bpp color depth 7. t10 = 9 for 4 bpp or 8 bpp color depth = 8 for 16 bpp color depth EPSON 1-64 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 77: Tft/D-Tfd Panel Timing
= (REG[03Ah] bits [5:0]) + 1 = ((REG[032h] bits [6:0]) + 1) × 8Ts = Horizontal Display Period = ((REG[034h] bits [4:0]) + 1) × 8Ts HNDP = Horizontal Non-Display Period = HNDP + HNDP EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-65 SPECIFICATION (X28B-A-001-03)
Page 78: Figure 6-33 Tft/D-Tfd A.c. Timing
FPSHIFT R[5:1] Invalid G[5:0] B[5:1] DRDY FPSHIFT R[5:1] 637, 1, 2 3, 4 639, 640 Invalid G[5:0] B[5:1] Note: DRDY is used to indicate the active display Figure 6-33 TFT/D-TFD A.C. Timing EPSON 1-66 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 79 = [((REG[034h] bits [4:0]) + 1) × 8 - (REG[035h] bits [4:0]) × 8 - 5] for 16 bpp color depth = [(REG[035h] bits [4:0]) × 8 + 4] for 4 bpp or 8 bpp color depth 13. t27 = [(REG[035h] bits [4:0]) × 8 + 5] for 16 bpp color depth EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-67 SPECIFICATION (X28B-A-001-03)
Page 80: Crt Timing
= ((REG[052h] bits [5:0]) + 1) × 8Ts = (REG[053h] bits [5:0]) × 8 + 4Ts for 4/8 bpp HNDP = HRTC Start Position = (REG[053h] bits [5:0]) × 8 + 5Ts for 16 bpp EPSON 1-68 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 81: Figure 6-35 Crt A.c. Timing
= [((REG[057h] bits 1:0, REG[056h] bits 7:0) + 1) + ((REG[058h] bits 6:0) + 1)] 2. t2 = [((REG[05Ah] bits 2:0) + 1)] = [((REG[053h] bits 4:0) + 1) × 8] 3. t3 EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-69 SPECIFICATION (X28B-A-001-03)
Page 82: Tv Timing
1 VNDP TV VRTC Start Position (field 1) Field 2 start of field 2 VNDP TV VRTC Start Position (field 2) Start of Vertical Sync Figure 6-36 NTSC Video Timing EPSON 1-70 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 83 311 312 313 314 315 316 317 318 319 320 334 335 336 Field 4 start of field 4 VNDP TV VRTC Start Position (field 4) Start of Vertical Sync Figure 6-37 PAL Video Timing EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-71 SPECIFICATION (X28B-A-001-03)
Page 84 For NTSC, (((REG[050] bits[6:0]) + 1) × 8) + (((REG[052] bits[5:0]) × 8) + 6) = 910. For PAL, (((REG[050] bits[6:0]) + 1) × 8) + (((REG[052] bits[5:0]) × 8) + 7) = 1135. EPSON 1-72 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 85 For NTSC, ({(REG[057] bits[1:0]), (REG[056] bits[7:0])} + 1) + ((REG[058] bits[6:0]) + 1) × 2 + 1) = 525 For PAL, ({(REG[057] bits[1:0]), (REG[056] bits[7:0])} + 1) + ((REG[058] bits[6:0]) + 1) × 2 + 1) = 625. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-73 SPECIFICATION (X28B-A-001-03)
Page 86: Mediaplug Interface Timing
Output data delay from VMPCLK falling edge Output data tristate delay from VMPCLK falling edge Note: VMPCLK, VMPCLKN are twice the period of the MediaPlug Clock. See Section 7, “Clocks” on page EPSON 1-74 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 87: Clocks
REG[014h] bits 5,4 ÷2 CRT/TV ÷3 PCLK Enable ÷4 REG[018h] bits 1,0 REG[018h] bit 7 REG[018h] bits 5,4 ÷2 MediaPlug ÷3 Clock ÷4 REG[01Ch] bits 1,0 REG[01Ch] bits 5,4 Figure 7-1 Clock Overview Diagram EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-75 SPECIFICATION (X28B-A-001-03)
Page 88: Clock Descriptions
MediaPlug Clock must be in the range of 12-16MHz. For AC timing see Section 6.6, “MediaPlug Interface Timing” on page 74. VMPCLK (6-8MHz) MediaPlug Clock ÷2 (12-16MHz) VMPCLKN (6-8MHz) Figure 7-2 MediaPlug Clock Output Signals EPSON 1-76 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 89: Clock Selection
Note: 1. The CRT/TV pixel clock may be further multiplied by 2 when TV with Flicker Filter is enabled using REG[018h] bit 7. 2. MCLK may be a previously divided down version of CLKI, CLKI3, or BUSCLK. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-77 SPECIFICATION (X28B-A-001-03)
Page 90: Clocks Vs. Functions
MediaPlug Registers — — — read/write Power Save Mode see Section 19, “Power Save Mode” on page 181 Note: The S1D13806 contains sophisticated power management that dynamically shuts down clocks when not required. EPSON 1-78 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 91: Registers
To initialize the embedded SDRAM in the S1D13806, this bit must be set to 1 a minimum of 200µs after reset. This bit must be set to 1 before memory access is performed. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-79 SPECIFICATION (X28B-A-001-03)
Page 92: Register Mapping
1000h to 1FFFh On-chip registers (512 bytes) 0 to 1FFh Note: The registers may be aliased within the allocated register space. If aliasing is undesirable, the regis- ter space must be fully decoded. EPSON 1-80 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 93: Register Set
99 REG[07Ah] LCD Ink/Cursor Blue Color 1 Register REG[043h] LCD Display Start Address Register 1 99 REG[07Bh] LCD Ink/Cursor Green Color 1 Register REG[044h] LCD Display Start Address Register 2 99 REG[07Ch] LCD Ink/Cursor Red Color 1 Register EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-81 SPECIFICATION (X28B-A-001-03)
Page 94 REG[112h] BitBLT Height Register 0 REG[113h] BitBLT Height Register 1 REG[114h] BitBLT Background Color Register 0 REG[115h] BitBLT Background Color Register 1 REG[118h] BitBLT Foreground Color Register 0 REG[119h] BitBLT Foreground Color Register 1 EPSON 1-82 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 95: Register Descriptions
2 Reserved. This bit must be set to 0. bit 1 Reserved. This bit must be set to 0. bit 0 Reserved. This bit must be set to 0. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-83 SPECIFICATION (X28B-A-001-03)
Page 96: General Io Pins Registers
GPIO[n] high and writing a 0 to this bit drives GPIO[n] low. (n ranges from 0 to 7) When GPIO[n] is configured as an input, a read from bit n returns the status of GPIO[n]. (n ranges from 0 to 7) EPSON 1-84 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 97: Configuration Readback Register
When this bit = 0, the memory clock frequency is equal to the MCLK source frequency. Note: The MCLK frequency should always be set to the maximum frequency allowed by the SDRAM. This provides maximum performance and minimizes overall system power consumption. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-85 SPECIFICATION (X28B-A-001-03)
Page 98 These bits determine the divide used to generate the LCD pixel clock from the LCD pixel clock source. Table 8-5 LCD PCLK Divide Selection LCD PCLK Divide Select Bits LCD PCLK Source to LPCLK Frequency Ratio EPSON 1-86 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 99 These bits determine the divide used to generate the CRT/TV pixel clock from the CRT/TV pixel clock source. Table 8-7 CRT/TV PCLK Divide Selection CRT/TV PCLK Divide Select Bits CRT/TV PCLK Source to DPCLK Frequency Ratio EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-87 SPECIFICATION (X28B-A-001-03)
Page 100 These bits determine the divide used to generate the MediaPlug Clock from the MediaPlug Clock source. Table 8-9 MediaPlug Clock Divide Selection MediaPlug Clock Source to MediaPlug Clock MediaPlug Clock Divide Select Bits Frequency Ratio EPSON 1-88 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 101 Failure to meet the following conditions may lead to system crash which is recoverable only by RESET. Table 8-11 Minimum Memory Timing Selection Wait State Bits [1:0] Condition no restrictions × period (MCLK) - 4ns > period(BCLK) period(MCLK) - 4ns > period(BCLK) Reserved EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-89 SPECIFICATION (X28B-A-001-03)
Page 102: Memory Configuration Registers
Table 8-12 SDRAM Refresh Rate Selection SDRAM Refresh MCLK Source Frequency (MHz) Rate Bits [2:0] 4.096 <= MClk < 8.192 8.192 <= MClk < 16.384 16.384 <= MClk < 32.768 32.768 <= MClk <= 50.000 EPSON 1-90 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 103: Panel Configuration Registers
When this bit = 1, the TFT 2x Data format is selected. When this bit = 0, the standard TFT Data format is selected. For details on the TFT 2x Data format, see Section 6.4.10, “TFT/D-TFD Panel Timing” on page 65. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-91 SPECIFICATION (X28B-A-001-03)
Page 104 For a non-zero value these bits specify the number of FPLINE between toggles of the MOD output signal (DRDY). When these bits are all 0’s the MOD output signal toggles every FPFRAME. These bits are for passive LCD panels only. EPSON 1-92 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 105 HNDP width in number of pixels = ((ContentsOfThisRegister) + 1) × 8 Note: This register must be programmed such that REG[034h] ≥ 3 (32 pixels). Note: For TFT/D-TFD only: REG[034h] + 1 ≥ (REG[035h] + 1) + (REG[036h] bits 3-0 + 1) EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-93 SPECIFICATION (X28B-A-001-03)
Page 106 When this bit = 0, the FPLINE pulse is active low for TFT/D-TFD and active high for passive LCD. Table 8-16 LCD FPLINE Polarity Selection LCD FPLINE Polarity Select Passive LCD FPLINE Polarity TFT FPLINE Polarity active high active low active low active high EPSON 1-94 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 107 Vertical non-display period height in number of lines = (ContentsOfThis- Register) + 1 Note: For TFT/D-TFD only: (REG[03Ah] bits 5-0 + 1) ≥ (REG[03Bh] + 1) + (REG[03Ch] bits 2-0 + 1) EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-95 SPECIFICATION (X28B-A-001-03)
Page 108 FPFRAME output signal in number of lines. FPFRAME pulse width in number of lines = (ContentsOfThisRegister) + 1 Note: (REG[03Ah] bits 5-0 + 1) ≥ (REG[03Bh] + 1) + (REG[03Ch] bits 2-0 + 1) EPSON 1-96 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 109: Lcd Display Mode Registers
REG[041h] bit 1). TFT/D-TFD panels support up to 64K colors. Table 8-19 LCD Bit-per-pixel Selection Bit-per-pixel Select Bits [1:0] Color Depth (bpp) 000-001 Reserved 4 bpp 8 bpp Reserved 16 bpp 110-111 Reserved EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-97 SPECIFICATION (X28B-A-001-03)
Page 110 However, disabling the dual panel buffer reduces image contrast and overall display quality. For details on Frame Rate Cal- culation, see Section 18, “Clocking” on page 169. EPSON 1-98 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 111 “n” to the starting word of line “n + 1”. A virtual image can be formed by setting this register to a value greater than the width of the display. The displayed image is a window into the larger virtual image. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-99 SPECIFICATION (X28B-A-001-03)
Page 112 Note: This register does not need to be used in single display modes and may only be required in some dis- play modes where two displays are active (see Section 16.3, “Bandwidth Limitation” on page 167). EPSON 1-100 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 113: Crt/Tv Configuration Registers
Note: For CRT, the recommended minimum value which should be programmed into this register is 3 (32 pixels). Note: REG[052h] + 1 ≥ (REG[053h] + 1) + (REG[054h] bits 3-0 + 1) EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-101 SPECIFICATION (X28B-A-001-03)
Page 114 HRTC pulse width in number of pixels = ((ContentsOfThisRegister) + 1) × Note: For TV, these bits must be set to 0. Note: REG[052h] + 1 ≥ (REG[053h] + 1) + (REG[054h] bits 3-0 + 1) EPSON 1-102 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 115 These bits specify the CRT/TV vertical non-display period height in 1 line resolution. Vertical non-display period height in number of lines = (ContentsOfThis- Register) + 1 Note: (REG[058h] bits 6-0 + 1) ≥ (REG[059h] + 1) + (REG[05Ah] bits 2-0 + 1) EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-103 SPECIFICATION (X28B-A-001-03)
Page 116 VRTC pulse width in number of lines = (ContentsOfThisRegister) + 1 Note: For TV, these bits must be set to 0. Note: (REG[058h] bits 6-0 + 1) ≥ (REG[059h] + 1) + (REG[05Ah] bits 2-0 + 1) EPSON 1-104 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 117 When this bit = 1, PAL format TV signal output is selected. When this bit = 0, NTSC format TV signal output is selected. This bit must be set to 0 when CRT is enabled. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-105 SPECIFICATION (X28B-A-001-03)
Page 118: Crt/Tv Display Mode Registers
Note: Color depth of 16 bpp bypasses the LUT and support up to 64K colors on the CRT/TV. Table 8-22 CRT/TV Bit-per-pixel Selection Bit-per-pixel Select Bits 1:0 Color Depth (bpp) Reserved Reserved 4 bpp 8 bpp Reserved 16 bpp 110-111 Reserved EPSON 1-106 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 119 “n” to the starting word of line “n + 1”. A virtual image can be formed by setting this register to a value greater than the width of the dis- play. The displayed image is a window into the larger virtual image. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-107 SPECIFICATION (X28B-A-001-03)
Page 120 Note: This register does not need to be used in single display modes and may only be required in some dis- play modes where two displays are active (see Section 16.3, “Bandwidth Limitation” on page 167). EPSON 1-108 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 121: Lcd Ink/Cursor Registers
These bits enable the LCD Ink/Cursor circuitry. Table 8-24 LCD Ink/Cursor Selection LCD Ink/Cursor Bits [1:0] Mode Inactive Cursor Reserved Note: While in Ink mode, the Cursor X and Y Position registers must be set to 00h. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-109 SPECIFICATION (X28B-A-001-03)
Page 122 When this bit = 1, it defines the LCD Cursor X Position register to be a negative number. The negative number shall not exceed 63 decimal. When this bit = 0, it defines the LCD Cursor X Position register to be a positive number. EPSON 1-110 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 123 Color 0 Bit 3 Color 0 Bit 2 Color 0 Bit 1 Color 0 Bit 0 bits 4-0 LCD Ink/Cursor Blue Color 0 Bits[4:0] These bits define the blue LCD Ink/Cursor color 0. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-111 SPECIFICATION (X28B-A-001-03)
Page 124 Color 1 Bit 3 Color 1 Bit 2 Color 1 Bit 1 Color 1 Bit 0 bits 4-0 LCD Ink/Cursor Red Color 1 Bits[4:0] These bits define the red LCD Ink/Cursor color 1. EPSON 1-112 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 125: Crt/Tv Ink/Cursor Registers
These bits enable the CRT/TV Ink/Cursor circuitry. Table 8-26 CRT/TV Ink/Cursor Selection CRT/TV Ink/Cursor Bits [1:0] Mode Inactive Cursor Reserved Note: While in Ink mode, the Cursor X and Y Position registers must be set to 00h. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-113 SPECIFICATION (X28B-A-001-03)
Page 126 = 255...161 Invalid Note: The effect of this register takes place at the next CRT/TV vertical non-display period. Note: See Section 10, “Display Buffer” on page 137 for display buffer organization. EPSON 1-114 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 127 When this bit = 1, it defines the CRT/TV Cursor Y Position register to be a negative number. The negative number shall not exceed 63 decimal. When this bit = 0, it defines the CRT/TV Cursor Y Position register to be a positive number. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-115 SPECIFICATION (X28B-A-001-03)
Page 128 Color 1 Bit 3 Color 1 Bit 2 Color 1 Bit 1 Color 1 Bit 0 bits 4-0 CRT/TV Ink/Cursor Blue Color 1 Bits[4:0] These bits define the blue CRT/TV Ink/Cursor color 1. EPSON 1-116 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 129 Cursor These bits are used to optimize the display memory request arbitration for the Hardware Cursor/Ink Layer. When this register is set to 00h, the thresh- old is automatically set in hardware. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-117 SPECIFICATION (X28B-A-001-03)
Page 130: Bitblt Configuration Registers
BitBLT FIFO Not Number of Words Full Status Full Status Empty Status available in BitBLT (REG[100h] Bit 4) (REG[100h] Bit 5) (REG[100h] Bit 6) FIFO 1 to 6 7 to 14 15 to 16 EPSON 1-118 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 131 This bit selects the color format that the 2D operation is applied to. When this bit = 0, 8 bpp (256 color) format is selected. When this bit = 1, 16 bpp (64K color) format is selected. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-119 SPECIFICATION (X28B-A-001-03)
Page 132 S + ~D P + ~D bit 5 1110 S + D P + D bit 6 1111 1 (Whiteness) 1 (Whiteness) bit 7 Note: S = Source, D = Destination, P = Pattern. EPSON 1-120 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 133 Note: The BitBLT operations Pattern Fill with ROP and Pattern Fill with transparency require a BitBLT width > 2 for 8 bpp color depths and a BitBLT width > 1 for 16 bpp color depths. The BitBLT width is set in REG[110h], REG[111h]. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-121 SPECIFICATION (X28B-A-001-03)
Page 134 BitBLT Source Start Address[20:7] BitBLT Source Start Address[6:4] BitBLT Source Start Address[3:0] Note: For further information on the BitBLT Source Start Address register, see the S1D13806 Programming Notes and Examples, document number X28B-G-003-xx. EPSON 1-122 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 135 + 1. They are used only for address cal- culation when the BitBLT is configured as a rectangular region of memory. They are not used for the displays. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-123 SPECIFICATION (X28B-A-001-03)
Page 136 Bit 8 REG[112h] bits 7-0 BitBLT Height Bits [9:0] REG[113h] bits 1-0 A 10-bit register that specifies the BitBLT height in lines - 1. BitBLT height in lines = (ContentsOfThisRegister) + 1 EPSON 1-124 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 137 Expansion or Solid Fill. For 16 bpp color depths (REG[101h] bit 0 = 1), all 16 bits are used. For 8 bpp color depths (REG[101h] bit 0 = 0), only bits 7- 0 are used. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-125 SPECIFICATION (X28B-A-001-03)
Page 138: Look-Up Table Registers
Data Register move the pointer onto B[3], R[4], G[4], B[4], R[5], etc. Note: The RGB data is inserted into the LUT after the Blue data is written, i.e. all three colors must be writ- ten before the LUT is updated. EPSON 1-126 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 139: Power Save Configuration Registers
When this bit = 1, power save mode is enabled. When this bit = 0, power save mode is disabled. Note: For details on Power Save Mode, see Section 19, “Power Save Mode” on page 181. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-127 SPECIFICATION (X28B-A-001-03)
Page 140 When this bit = 0, the memory controller is powered up and is in normal mode. Note: When this bit reads a 1, the system may safely shut down the memory clock source. EPSON 1-128 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 141: Miscellaneous Registers
CPU-to-memory access cycle time in order gain higher CPU bandwidth. Doing so may significantly reduce the available display refresh bandwidth which may cause display corruption. This regis- ter does not affect CPU-to-register access or BitBLT access. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-129 SPECIFICATION (X28B-A-001-03)
Page 142: Common Display Mode Register
(1 vertical pixel). For example, one pixel high lines, edges of window boxes, etc. Flickering occurs because these high resolution lines are effectively displayed at half the refresh frequency due to interlacing. EPSON 1-130 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 143: Mediaplug Registers Descriptions
Write Xxxx Read Rstat[2:0] bits 15-14 Timeout Option These bits select the timeout delay in MediaPlug clock cycles. Table 8-37 Timeout Option Delay Timeout Option Bits[15:14] Timeout (MediaPlug clock cycles) 1023 (default) EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-131 SPECIFICATION (X28B-A-001-03)
Page 144 When this bit = 1, power to remote is on. bit 0 Watchdog Disable When this bit = 0, the MediaPlug watchdog is enabled (default). When this bit = 1, the MediaPlug watchdog is disabled. EPSON 1-132 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 145 3. Write to DATA register if the CCC field is Write_Reg. 4. Read to DATA register if the CCC field is Read_Reg. It is also set when the Remote Machine loses power or the cable is discon- nected. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-133 SPECIFICATION (X28B-A-001-03)
Page 146 This register is not implemented and is reserved for future expansion of the CMD register. A write to this register has no hardware effect. A read from this register always return 0000h. EPSON 1-134 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 147: Mediaplug Data Registers
Data Bit 10 Data Bit 9 Data Bit 8 Data Register bits 15-0 BitBLT Data Bits [15:0] A 16-bit register that specifies the BitBLT data. This register is loosely decoded from 100000h to 1FFFFEh. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-135 SPECIFICATION (X28B-A-001-03)
Page 148: Bit Blt Engine
• Transparent Move BitBLT. • Read BitBLT. • Color Expansion BitBLT. • Move BitBLT with Color Expansion. Note: For details on the BitBLT registers, see Section 8.4.12, “BitBLT Configuration Registers” on page 118. EPSON 1-136 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 149: Display Buffer
The display buffer can contain an image buffer, one or more Ink Layer/Hardware Cursor buffers, and a dual panel buffer. AB[20:0] 1280k Byte Buffer 00 0000h Image Buffer Ink/Cursor Buffer 13 FFFFh Dual Panel Buffer 14 0000h Unavailable 1F FFFFh Figure 10-1 Display Buffer Addressing EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-137 SPECIFICATION (X28B-A-001-03)
Page 150: Image Buffer
For a 800 × 600 color panel the dual panel buffer size is 120,000 bytes. With a 1280k byte display buffer, the dual panel buffer resides from 12 2b40h to 13 FFFFh. EPSON 1-138 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 151: Display Configuration
Figure 11-1 4/8/16 Bit-per-pixel Format Memory Organization Note: 1. The Host-to-Display mapping shown here is for a little endian system. 2. For the 16 bit-per-pixel format, R represent the red, green, and blue color components. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-139 SPECIFICATION (X28B-A-001-03)
Page 152: Image Manipulation
LCD display. The screen image on the CRT/TV is manipulated similarly. When EISD is enabled (see Section 16, “EPSON Independent Simultaneous Display (EISD)” on page 166), the images on the LCD and on the CRT/TV are independent of each other.
Page 153: Look -U P Table Architecture
A color depth of 16 bpp is required to achieve 64 gray shades in monochrome mode. In this mode the LUT is bypassed and the green component of the pixel is mapped to the FRM. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-141 SPECIFICATION (X28B-A-001-03)
Page 154: Color Modes
0001 (01h) 0101 (05h) to display Blue Look-Up Table 256x4 4-bit Blue Data: example data: 0001 (01h) 1111 (0Fh) = unused Look-Up Table entries Figure 12-2 4 Bit-Per-Pixel Color Mode Data Output Path EPSON 1-142 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 155 Figure 12-3 8 Bit-Per-Pixel Color Mode Data Output Path 16 Bit-Per-Pixel Color Modes The LUT is bypassed and the color data is directly mapped for this color mode – Section 11, “Dis- play Configuration” on page 139. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-143 SPECIFICATION (X28B-A-001-03)
Page 156: Tv Considerations
The required clock frequencies for NTSC/PAL are given in the following table. Table 13-1 Required Clock Frequencies for NTSC/PAL TV Format Required Clock Frequency NTSC 14.318180 MHz (3.579545 MHz subcarrier) 17.734475 MHz (4.43361875 MHz subcarrier) EPSON 1-144 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 157: Filters
Flickering occurs because these high resolution lines are effectively displayed at half the refresh fre- quency due to interlacing. The anti-flicker filter averages adjacent lines on the TV display to reduce flickering. This filter is controlled using the Display Mode register (REG[1FCh] bits [2:1]). EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-145 SPECIFICATION (X28B-A-001-03)
Page 158: Tv Output Levels
1F 00 00 Blue 00 00 1F blue Black 00 00 00 black Blanking N.A. blanking Sync Tip N.A. sync Note: RGB values assume a 16 bpp color depth with 5-6-5 pixel packing. EPSON 1-146 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 159 Magenta negative peak 1F 00 1F magenta Red negative peak 1F 00 00 Blue negative peak 00 00 1F -40.8 blue Note: RGB values assume a 16 bpp color depth with 5-6-5 pixel packing. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-147 SPECIFICATION (X28B-A-001-03)
Page 160 20 / 18 burst Burst negative peak N.A. 142 / 153 -20 / -19 burst Sync Tip N.A. sync Note: RGB values assume a 16 bpp color depth with 5-6-5 pixel packing. EPSON 1-148 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 161: Tv Image Display And Positioning
The maximum and minimum register values for these registers are given in Table 13-5, “Minimum and Maximum Values for NTSC/PAL TV”. Increasing the HRTC Start Position moves the image left, while increasing the VRTC Start Position moves the image up. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-149 SPECIFICATION (X28B-A-001-03)
Page 162 Note: The TV Vertical Non-Display Period (t5) varies by 1 line depending on the field that it follows. Note: For NTSC panels the minimum and maximum values will vary for each application. EPSON 1-150 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 163: Tv Cursor Operation
TV Horizontal Non-Display Period TV HRTC Start Position TV Vertical Display Height TV Vertical Non-Display Period TV Vertical Start Position 13.4.2 TV Cursor Operation See Section 14, “Ink Layer/Hardware Cursor Architecture” on page 152. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-151 SPECIFICATION (X28B-A-001-03)
Page 164: Ink Layer /Hardware Cursor Architecture
LCD Ink Address Offset (words) = REG[032h] + 1 CRT/TV Ink Address Offset (words) = REG[050h] + 1 LCD or CRT/TV Cursor Address Offset (words) = 8 EPSON 1-152 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 165: Ink/Cursor Data Format
REG[088h], REG[087h], REG[086h] for CRT/TV) Ink/Cursor Color 1 Register, (REG[07Ah], REG[07Bh],REG[07Ah] for Color 1 LCD, REG[08Ah], REG[08Bh], REG[08Ah] for CRT/TV) Background Ink/Cursor is transparent – show background Inverted Background Ink/Cursor is transparent – show inverted background EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-153 SPECIFICATION (X28B-A-001-03)
Page 166: Ink/Cursor Image Manipulation
= (REG[075h] bits [1:0], REG[074h]) and REG[075h] bit 7 = 0 For CRT/TV: x = (REG[083h] bits [1:0], REG[082h]) and REG[083h] bit 7 = 0 y = (REG[085h] bits [1:0], REG[084h]) and REG[085h] bit 7 = 0 EPSON 1-154 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 167 = (REG[075h] bits [1:0], REG[074h]) <= 63 and REG[075h] bit 7 = 1 For CRT/TV: x = (REG[083h] bits [1:0], REG[082h]) <= 63 and REG[083h] bit 7 = 1 y = (REG[085h] bits [1:0], REG[084h]) <= 63 and REG[085h] bit 7 = 1 EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-155 SPECIFICATION (X28B-A-001-03)
Page 168: Swivel View
However, it is still possible to pan and scroll the portrait window in 90° Swivel- View, but the user must program these registers somewhat differently (See Section 15.2.1, “Register Programming” on page 157). EPSON 1-156 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 169: Register Programming
The LCD Memory Address Offset register (REG[046h], REG[047h]) must be set for a 1024 pixel offset: LCD Memory Address Offset (words) = 1024 for 16 bpp color depth = 512 for 8 bpp color depth EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-157 SPECIFICATION (X28B-A-001-03)
Page 170 = (1024 - W) for 16 bpp color depth = (1024 - W) / 2 for 8 bpp color depth where W is the width of the panel in number of pixels. EPSON 1-158 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 171: Physical Memory Requirement
Ink Layer, Hardware Cursor, or even the CRT/TV display buffer. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-159 SPECIFICATION (X28B-A-001-03)
Page 172 640 - 600 = 40 pixels. The programmer also should not read/write to the memory beyond the maximum accessible horizontal virtual size because that memory is either reserved for the dual panel buffer or not associated with any real memory at all. EPSON 1-160 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 173 8 bpp 600KB Mono 29.30KB — /1248KB 16 bpp 1.2MB × Note: 1. 800 600 color 16bpp dual panel is not supported. Note: Where KB = 1024 bytes, and MB = 1024K bytes. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-161 SPECIFICATION (X28B-A-001-03)
Page 174: Limitations
H is the height of the panel in number of lines, W is the width of the panel in number of pix- els, and MA_Offset is the LCD Memory Address Offset. EPSON 1-162 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 175: Limitations
The LCD Memory Address Offset register (REG[046h], REG[047h]) must be set for a 1024 pixel offset. LCD Memory Address Offset (words) = 1024 for 16 bpp color depth = 512 for 8 bpp color depth EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-163 SPECIFICATION (X28B-A-001-03)
Page 176 • Increment/decrement LCD Display Start Address register in 16 bpp color depth scrolls the display window up/down by 1 line. • Increment/decrement LCD Pixel Panning register in 8 bpp color depth scrolls the display window down/up by 1 line. EPSON 1-164 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 177: Physical Memory Requirement
• For 270° SwivelView modes, BitBLT (Bit Block Transfer) operations are still supported. How- ever, the BitBLT data must first be rotated by software. For further information, refer to the “S1D13806 Programmers Notes And Examples,” document number X28B-G-003-xx. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-165 SPECIFICATION (X28B-A-001-03)
Page 178: Epson Independent Simultaneous Display (Eisd)
IMULTANEOUS (EISD) ISPLAY EPSON Independent Simultaneous Display (EISD) allows the S1D13806 to display independent images on two different displays (LCD panel and CRT or TV). 16.1 Registers The LCD panel timings and mode setup are programmed through the Panel Configuration Registers (REG[03Xh]) and the LCD Display Mode Registers (REG[04Xh]).
Page 179: Bandwidth Limitation
16: EPSON INDEPENDENT SIMULTANEOUS DISPLAY (EISD) 16.3 Bandwidth Limitation When EISD is enabled, the LCD and CRT/TV displays must share the total bandwidth available to the S1D13806. The result is that display modes with a high resolution or color depth may not be supported.
Page 180: Media Plug Interface
Pin Names VMP0 VMPCLKN VMP1 VMPCLK VMP2 VMPD3 VMP3 VMPD2 VMP4 VMPD1 VMP5 VMPD0 VMP6 VMPRCTL VMP7 VMPLCRL GPIO12 VMPEPWR Note: VMPEPWR is controlled by bit 1 of the MediaPlug LCMD register. EPSON 1-168 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 181: Clocking
= ((REG[032h] bits [6:0]) + 1) × 8Ts LHNDP = LCD Horizontal Non-Display Period = ((REG[034h] bits [4:0]) + 1) × 8Ts = minimum LCD pixel clock (LPCLK) period = 1 for single panel = 2 for dual panel EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-169 SPECIFICATION (X28B-A-001-03)
Page 182: Crt Frame Rate Calculation
= CRT Horizontal Display Width = ((REG[050h] bits [6:0]) + 1) × 8Ts CHNDP = CRT Horizontal Non-Display Period = ((REG[052h] bits [5:0]) + 1) × 8Ts = minimum CRT pixel clock (CPCLK) period EPSON 1-170 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 183: Tv Frame Rate Calculation
= TV Horizontal Non-Display Period = for NTSC output use ((REG[052h] bits [5:0]) × 8Ts) + 6 = for PAL output use ((REG[052h] bits [5:0]) × 8Ts) + 7 = minimum TV pixel clock (TPCLK) period EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-171 SPECIFICATION (X28B-A-001-03)
Page 184: Example Frame Rates
56.6 — — — — — — — — — — 17.73 56.6 — — — — — — — — — — 17.73 56.6 Example Frame Rates with Ink Layer Enabled EPSON 1-172 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 185 56.6 — — — — — — — — — — 17.73 56.6 — — — — — — — — — — 17.73 56.6 Example Frame Rates with Ink Layer Enabled EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-173 SPECIFICATION (X28B-A-001-03)
Page 186: Frame Rates For 800 ¥ 600 With Eisd Disabled
74.6 49.5 74.6 56.25 84.8 56.25 84.8 Example Frame Rates with Ink Layer Enabled The FIFO values for these display modes must be set as follows: REG[07Eh] = 0Ch. REG[08Eh] = 0Ah. EPSON 1-174 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 187: Frame Rates For 1024 ¥ 768 With Eisd Disabled
— — — — — — — — 1024 59.8 Example Frame Rates with Ink Layer Enabled The FIFO values for these display modes must be set as follows: REG[07Eh] = 0Ch. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-175 SPECIFICATION (X28B-A-001-03)
Page 188: Frame Rates For Lcd And Crt (640 ¥ 480) With Eisd Enabled
The FIFO values for these display modes must be set as follows: REG[06Ah] = 3Ch. REG[06Bh] = 3Ch. REG[08Eh] = 0Ch. REG[06Ah] = 3Ch. REG[06Bh] = 3Ch. REG[07Eh] = 0Ch. REG[08Eh] = 0Ch. EPSON 1-176 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 189: Frame Rates For Lcd And Crt (800 ¥ 600) With Eisd Enabled
The FIFO values for these display modes must be set as follows: REG[04Ah] = 30h. REG[06Ah] = 30h. REG[04Bh] = 3Ch. REG[06Bh] = 3Ch. REG[04Ah] = 1Ah. REG[06Bh] = 25h. REG[06Ah] = 23h. REG[08Eh] = 0Ch. REG[08Eh] = 0Ch. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-177 SPECIFICATION (X28B-A-001-03)
Page 190: Frame Rates For Lcd And Crt (1024 ¥ 768) With Eisd Enabled
The FIFO values for these display modes must be set as follows: REG[04Ah] = 25h. REG[04Bh] = 3Ch. REG[06Ah] = 30h. REG[06Bh] = 3Ch. REG[04Ah] = 1Ah. REG[06Ah] = 30h. REG[06Bh] = 3Ch. REG[07Eh] = 0Ch. EPSON 1-178 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 191: Frame Rates For Lcd And Ntsc Tv With Eisd Enabled
14.32 62.7 Color Passive Dual NTSC 14.2 81.8 14.32 62.7 Example Frame Rates with Ink Layer Enabled The FIFO values for these display modes must be set as follows: REG[07Eh] = 0Ch. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-179 SPECIFICATION (X28B-A-001-03)
Page 192: Frame Rates For Lcd And Pal Tv With Eisd Enabled
12.3 72.5 17.73 56.6 Example Frame Rates with Ink Layer Enabled The FIFO values for these display modes must be set as follows: REG[04Ah] = 3Ch. REG[04Bh] = 3Ch. REG[07Eh] = 7Ch. EPSON 1-180 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 193: Power Save Mode
0, the SDRAM interface is active. The system may disable the memory clock source when this bit returns a 1. The Memory Controller Power Save Status bit is set to 0 after chip reset. EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-181 SPECIFICATION (X28B-A-001-03)
Page 194: Power Save Mode Summary
Forced Low — Forced Low CRT/TV interface — Disabled Disabled SDRAM interface Active Active Self-Refresh Host Interface Active Active Active Note: 1. LCD pixel clock required. Note: 2. CRT/TV pixel clock required. EPSON 1-182 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 195: Mechanical Data
20: MECHANICAL DATA 20 M ECHANICAL 144-pin QFP20 surface mount package Unit: mm ±0.4 22.0 ±0.1 20.0 Index +0.1 -0.05 +0.05 -0.025 0.125 0° 10° ±0.2 Figure 20-1 Mechanical Drawing 144-pin QFP20 EPSON S1D13806 SERIES HARDWARE FUNCTIONAL 1-183 SPECIFICATION (X28B-A-001-03)
Page 196 20: MECHANICAL DATA THIS PAGE IS BLANK. EPSON 1-184 S1D13806 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X28B-A-001-03)
Page 198 Move Cursor in SwivelView 90° Rotation..............2-43 8.5.3 Move Cursor in SwivelView 180° Rotation............... 2-43 8.5.4 Move Cursor in SwivelView 270° Rotation............... 2-44 ™ ........................2-45 WIVEL S1D13806 SwivelView ......................2-45 Registers ........................... 2-46 Limitations ..........................2-47 Examples ..........................2-48 EPSON S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES...
Page 199 11.2.3 TV Filters ......................... 2-88 11.2.4 Examples ......................... 2-89 11.3 Simultaneous Display ....................... 2-89 12 M ...........................2-90 EDIA 12.1 Programming ..........................2-90 12.2 Considerations .......................... 2-91 13 I S1D13806 ....................2-92 DENTIFYING THE EPSON 2-ii S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES...
Page 200 BitBLT Source Start Address Selection................2-54 Table 10-4 Possible BitBLT FIFO Writes....................2-60 Table 10-5 Possible BitBLT FIFO Writes....................2-65 Table 10-6 Possible BitBLT FIFO Writes....................2-73 Table 10-7 Possible BitBLT FIFO Reads ..................... 2-84 EPSON S1D13806 SERIES PROGRAMMING NOTES 2-iii AND EXAMPLES...
Page 201: Introduction
Power-on Initialization, Panning and Scrolling, LUT initialization, LCD Power Sequencing, SwivelView™, etc. This document will be updated as appropriate. Please check the latest revision of this document and source before beginning any development. EPSON S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 202: Initialization
Program CPU Wait States. see REG[01Eh] for details [020h] 1000 0000 Program the Frame Buffer Memory Configuration Registers. [021h] 0000 0100 see REG[020h] - REG[02Bh] for details [02Ah] 0000 0000 [02Bh] 0000 0001 EPSON S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 203 0000 0000 [063h] 0000 0000 For this example, these values are = don’t care. [064h] 0000 0000 [066h] 0000 0000 [067h] 0000 0000 [068h] 0000 0000 [06Ah] 0000 0000 [06Bh] 0000 0000 EPSON S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 204 0000 0000 are = don’t care. [084h] 0000 0000 [085h] 0000 0000 [086h] 0000 0000 [087h] 0000 0000 [088h] 0000 0000 [08Ah] 0000 0000 [08Bh] 0000 0000 [08Ch] 0000 0000 [08Eh] 0000 0000 EPSON S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 205 For this example, enable the LCD panel only. Note that the LCD [1FCh] 0000 0001 see REG[1FCh] Power Sequencing procedures outlined in Section 7.1, “Enabling the LCD Panel” should be used when enabling the LCD panel. EPSON S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 206: Memory Models
16 elements of the green component of the Look-Up Table (LUT). For color panels the 16 colors are derived by indexing into the first 16 positions of the LUT. EPSON S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 207: Memory Organization For 8 Bpp (256 Colors/16 Gray Shades)
The green indices, with only four bits, can resolve 16 gray shades. Note: When a monochrome panel (REG[030h] bit 2 = 0) is selected, a four bpp color depth also provides 16 gray shades and uses less display buffer. EPSON S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 208: Memory Organization For 16 Bpp (65536 Colors/64 Gray Shades)
Should monochrome mode be chosen at this color depth, the output sends the six bits of the green LUT component to the modulator for a total of 64 possible gray shades. If dithering is disabled, the maximum number of gray shades is 16. EPSON S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 209: Look -U P Table (Lut)
REG[1E2h] and REG[1E4h]. LUT mode selection allows the LUTs to be individually written or have identical data written to both LUTs. Individual writes to these registers are useful for Epson Independent Simultaneous Display (EISD) modes where independent images are displayed on the LCD and the CRT/TV.
Page 210: Look-Up Table Organization
4 bpp color 16 colors 16 colors 8 bpp color 256 colors 256 colors 16 bpp color 4096 colors 65536 colors = Indicates the Look-Up Table is not used for that display mode EPSON 2-10 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 211: Color Modes
The following table shows LUT values that will simulate those of a VGA operating in 16 color mode. Table 4-2 Suggested LUT Values to Simulate VGA Default 16 Color Palette Index Green Blue = Indicates unused entries in the LUT EPSON S1D13806 SERIES PROGRAMMING NOTES 2-11 AND EXAMPLES (X28B-G-003-01)
Page 212 The following table shows LUT values that will approximate the VGA default color palette. Table 4-3 Suggested LUT Values to Simulate VGA Default 256 Color Palette Index Index Index Index EPSON 2-12 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 213 Table 4-3 Suggested LUT Values to Simulate VGA Default 256 Color Palette (Continued) Index Index Index Index 16 bpp color The Look-Up Table is bypassed at this color depth, hence programming the LUT is not required. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-13 AND EXAMPLES (X28B-G-003-01)
Page 214: Gray Shade Modes
As with 8 bpp there are limitations to the colors which can be displayed. In this mode the six bits of green are used to set the absolute intensity of the image. This results in 64 gray shades when dither- ing is enabled and 16 gray shades when dithering is disabled. EPSON 2-14 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 215: Virtual Displays
640 × 480 pixels can be viewed by navigating a 320 × 240 pixel viewport around the image using panning and scrolling. 320 × 240 Viewport 640 × 480 “Virtual” Display Figure 5-1 Viewport Inside a Virtual Display EPSON S1D13806 SERIES PROGRAMMING NOTES 2-15 AND EXAMPLES (X28B-G-003-01)
Page 216: Registers
If PixelsPerVirtualLine equals the physical display width as set in the LCD Horizontal Display Width register (REG[032h]), then the virtual display and physical display are the same size. EPSON 2-16 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 217: Examples
= 190h words For the LCD, REG[047h] is set to 01h and REG[046h] is set to 90h. For the CRT/TV, REG[067h] is set to 01h and REG[066h] is set to 90h. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-17 AND EXAMPLES (X28B-G-003-01)
Page 218 = 200 × 2 × 600 = 240,000bytes The S1D13806 contains 1.25M bytes of embedded SDRAM (or 1,310,720bytes). As long as the calculated value is less than this, it is safe to continue with these values. EPSON 2-18 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 219: Panning And Scrolling
2. Update the start address registers - For the LCD, REG[042h], REG[043h], REG[044h]; for the CRT/TV, REG[062h], REG[063h], REG[064h]. 3. Update the pixel panning register - For the LCD, REG[048h] bits 1-0; for the CRT/TV REG[068h] bits 1-0. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-19 AND EXAMPLES (X28B-G-003-01)
Page 220: Registers
The following table lists the maximum number of pixels affected by a change of one to these registers. Table 5-1 Number of Pixels Panned When Start Address Changed By 1 Color Depth (bpp) Pixels per Word Number of Pixels Panned EPSON 2-20 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 221 4. Pan right by 1 pixel - reset the pixel panning register to 0: REG[048h] = 00b. - increment the start address register by 1: (REG[042h], REG[043h], REG[044h]) + 1. Note: The above example assumes the pixel panning register is initially set at 0. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-21 AND EXAMPLES (X28B-G-003-01)
Page 222: Examples
Note: Panning operations are easier to follow if a variable (e.g. PanValue) is used to track both the pixel panning and start address registers. The least significant bits of PanValue will represent the pixel panning register value and the more significant bits are the start address register value. EPSON 2-22 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 223 For the CRT/TV, REG[064h] is set to 00h, REG[063h] is set to 00h, and REG[062h] is set to C8h. Note: The above example assumes the display start address was initially 0 (the beginning of the display buffer). EPSON S1D13806 SERIES PROGRAMMING NOTES 2-23 AND EXAMPLES (X28B-G-003-01)
Page 224: Power Save Mode
Note: Bit 4 is a reserved bit and must be programmed to 1. Note: Enabling/disabling Power Save Mode requires proper LCD Power Sequencing. See Section 7, “LCD Power Sequencing” on page 27. EPSON 2-24 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 225: Power Save Status Bits
(the SDRAM is in self-refresh mode). When this bit returns a 0, the SDRAM inter- face is active. This bit will return a 0 after a chip reset. Note: The memory clock source may be disabled when this bit returns a 1. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-25 AND EXAMPLES (X28B-G-003-01)
Page 226: Enabling Power Save Mode
3. Wait the required delay time as specified in the LCD panel specification. 4. Enable GPIO11 to activate the LCD bias power. Note: The S5U13806B00C uses GPIO11 to control the LCD bias power supplies. Your system design may vary. EPSON 2-26 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 227: Lcd Power Sequencing
For further information on the availability of GPIO pins, see the “S1D13806 Hardware Functional Specification,” document num- ber X28B-A-001-xx. Note: REG[1F0h] bit 4 must be set to 1 for proper LCD power sequencing. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-27 AND EXAMPLES (X28B-G-003-01)
Page 228: Enabling The Lcd Panel
3. Disable the LCD signals - Set Display Mode Select bit 0 (REG[1FCh] bit 0) to 0. 4. At this time, the LCD pixel clock source may be disabled (Optional). Note the LUT must not be accessed if the pixel clock is not active. EPSON 2-28 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 229: Hardware Cursor /Ink Layer
Both the Hardware Cursor and the Ink Layer use the same pixel values to select colors. The Hard- ware Cursor requires 1024bytes of display buffer and the Ink Layer requires (display width × dis- play height ÷ 4) bytes of display buffer. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-29 AND EXAMPLES (X28B-G-003-01)
Page 230: Registers
Table 8-2 Cursor/Ink Start Address Encoding Ink/Cursor Start Address Bits [7:0] Start Address (Bytes) 1280K - 1024 1280K - (n × 8192) 01h - A0h A1h - FFh Invalid EPSON 2-30 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 231 Note: The cursor position is not updated until the Cursor Y Position Register 1 is written (REG[075h] or REG[085h]). When updating the cursor position, always update both the X and Y registers; X first and Y second. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-31 AND EXAMPLES (X28B-G-003-01)
Page 232 Note: The cursor position is not updated until the Cursor Y Position Register 1 is written (REG[075h] or REG[085h]). When updating the cursor position, always update both the X and Y registers; X first and Y second. EPSON 2-32 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 233 Red Color 1 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 These registers form the 16 bpp (5-6-5) RGB values of user-defined color 1 for the LCD Ink Layer/ Hardware Cursor. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-33 AND EXAMPLES (X28B-G-003-01)
Page 234 Red Color 1 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 These registers form the 16 bpp (5-6-5) RGB values of user-defined color 1 for the CRT/TV Ink Layer/Hardware Cursor. EPSON 2-34 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 235 REG[08Eh] determines the FIFO high threshold for the CRT/TV Hardware Cursor/Ink Layer. When this register is set to 00h, the threshold is automatically set in hardware. For further information, see the “13806 Hardware Functional Specification,” document number X28B-A-001-xx. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-35 AND EXAMPLES (X28B-G-003-01)
Page 236: Initialization
Note: The dual panel buffer always starts at (1280K - Dual Panel Buffer Size). The size of a hardware cursor is always 1024bytes. The size of the ink layer in bytes is (display width × display height ÷ 4). EPSON 2-36 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 237: Examples
Set Color 0 to black [078h] 0000 0000 [07Ah] 0001 1111 [07Bh] 0011 1111 Set Color 1 to white [07Ch] 0001 1111 [07Eh] 0000 0000 Set FIFO High Threshold to default EPSON S1D13806 SERIES PROGRAMMING NOTES 2-37 AND EXAMPLES (X28B-G-003-01)
Page 238 Set Color 0 to black [078h] 0000 0000 [07Ah] 0001 1111 [07Bh] 0011 1111 Set Color 1 to white [07Ch] 0001 1111 [07Eh] 0000 0000 Set FIFO High Threshold to default EPSON 2-38 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 239: Writing Cursor/Ink Layer Images
Ink/Cursor Color 1 Register: Color 1 For LCD, REG[07Ah], REG[07Bh],REG[07Ch]. For CRT/TV, REG[08Ah], REG[08Bh], REG[08Ch]. Background Ink/Cursor is transparent – show background Inverted Background Ink/Cursor is transparent – show inverted background EPSON S1D13806 SERIES PROGRAMMING NOTES 2-39 AND EXAMPLES (X28B-G-003-01)
Page 240: Cursor Image
Note this saves 8192bytes of display buffer, not 1024bytes, because the start address moves in steps of 8192bytes. EPSON 2-40 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 241: Ink Layer Image
Note: It is possible to use the same Ink Layer image for both LCD and CRT/TV displays. Program the LCD and CRT/TV Ink/Cursor Start Address registers (REG[071h] and REG[081h]) to the same location. This save some display buffer which would otherwise be used by a second Ink Layer. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-41 AND EXAMPLES (X28B-G-003-01)
Page 242: Cursor Movement
6. If y is negative, take the value of the most significant byte of abs(y) and logically OR with 80h. Write the result to Y Position Register 1. If y is positive, take the value of the most significant byte of abs(y) and write to Y Position Reg- ister 1. EPSON 2-42 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 243: Move Cursor In Swivelview 90° Rotation
8. If y2 is negative, take the value of the most significant byte of abs(y2) and logically OR with 80h. Write the result to Y Position Register 1. If y2 is positive, write the most significant byte of abs(y2) to Y Position Register 1. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-43 AND EXAMPLES (X28B-G-003-01)
Page 244: Move Cursor In Swivelview 270° Rotation
7. If y is negative, take the value of the most significant byte of abs(y) and logically OR with 80h. Write the result to X Position Register 1. If y is positive, write the most significant byte of abs(y) to X Position Register 1. EPSON 2-44 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 245: Swivel View
• The display start address is calculated differently when SwivelView is enabled. • Calculations that would result in panning in landscape mode, may result in scrolling when Swivel- View is enabled and vice-versa. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-45 AND EXAMPLES (X28B-G-003-01)
Page 246: Registers
SwivelView Enable Memory Address Offset Value Display Rotated Bit 1 Bit 0 16 bpp 8 bpp PW ÷ 2 0 degrees 90 degrees 1024 PW ÷ 2 180 degrees 270 degrees 1024 EPSON 2-46 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 247: Limitations
• It is not possible to rotate an already displayed image. The image must be redrawn. Note: Drawing into the Hardware Cursor/Ink Layer with SwivelView enabled requires disabling SwivelView, drawing in the Hardware Cursor/Ink Layer buffer, then re-enabling SwivelView. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-47 AND EXAMPLES (X28B-G-003-01)
Page 248: Examples
9: SWIVELVIEW™ 9.4 Examples Source code demonstrating various SwivelView rotations is provided in the file 13806swivel.c available on the internet at www.eea.epson.com. Example 7 Rotate Image 90° for a 640 × 480 display at a color depth of 8 bpp.
Page 249: Simultaneous Display Considerations
• When modifying the CRT display buffer, SwivelView Enable Bit 0 must be cleared and then restored when finished. The following demonstrates this principle. 1. Save SwivelView Bit 0 2. Clear SwivelView Bit 0 3. Draw the CRT/TV image 4. Restore the saved SwivelView Bit 0. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-49 AND EXAMPLES (X28B-G-003-01)
Page 250: Bit Blt Engine
When this bit is read, it returns the status of the BitBLT engine. When a read from this bit returns 0, the BitBLT engine is idle and is ready for the next operation. When a read from this bit returns a 1, the BitBLT engine is busy. EPSON 2-50 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 251 The BitBLT Source Linear Select bit specifies the storage method of the source BitBLT. If this bit = 0, the source BitBLT is stored as a rectangular region of memory. If this bit = 1, the source BitBLT is stored as a contiguous linear block of memory. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-51 AND EXAMPLES (X28B-G-003-01)
Page 252 1 (Whiteness) 1 (Whiteness) bit 7 S = Source, D = Destination, P = Pattern Operators: ~ = NOT, . = Logical AND, + = Logical OR, ^ = Logical XOR EPSON 2-52 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 253 Bit 19 Bit 16 The BitBLT Source Start Address Registers form a 21-bit register that specifies the source start address for the BitBLT operation selected by the BitBLT Operation Register (REG[103h]). EPSON S1D13806 SERIES PROGRAMMING NOTES 2-53 AND EXAMPLES (X28B-G-003-01)
Page 254 BitBLT operation selected by the BitBLT Operation Register (REG[103h]). The destination address represents the upper left corner of the BitBLT rectangle (lower right corner of the BitBLT rectangle for Move BitBLT in Negative Direction). EPSON 2-54 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 255 Bit 0 REG[113h] BitBLT Height Register 1 BitBLT BitBLT Height Height Bit 9 Bit 8 The BitBLT Height Registers form a 10-bit register that specifies the BitBLT height in pixels less 1. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-55 AND EXAMPLES (X28B-G-003-01)
Page 256 Color Expansion or the Solid Fill BitBLT. For 16 bpp color depth (REG[101h] bit 0 = 1), all 16 bits are used. For 8 bpp color depth (REG[101h] bit 0 = 0), only bits 7-0 are used. EPSON 2-56 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 257: Bitblt Descriptions
However, this is very much platform dependent and must be determined for each system. Note: When TV with flicker filter is enabled or simultaneous display is active, always test the FIFO status before reading from/writing to the FIFO. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-57 AND EXAMPLES (X28B-G-003-01)
Page 258: Write Bitblt With Rop
CPU instructions are acceptable. If a system is able to separate one DWORD write into two WORD writes and the CPU writes the low word before the high word, then 32-bit CPU instructions are ac- ceptable. Otherwise, 16-bit CPU instructions are required. EPSON 2-58 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 259 9. Calculate the number of WORDS the BitBLT engine expects to receive. = ((BLTWidth + 1 + SourcePhase) ÷ 2) × BLTHeight nWORDS = (100 + 1) ÷ 2 × 20 = 1000 = 3E8h EPSON S1D13806 SERIES PROGRAMMING NOTES 2-59 AND EXAMPLES (X28B-G-003-01)
Page 260 12. Once the BitBLT operation is finished, read one word from offset 0 in the BitBLT memory area to shutdown the BitBLT engine. Note: The order of register initialization is irrelevant as long as all relevant registers are programmed before the BitBLT is started. EPSON 2-60 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 261: Color Expand Bitblt
Source Address = 0 Start Bit Position = 7 (bit seven of the low byte) BitBLT Width = 16 The following bits are expanded. Word Sent To BitBLT Engine High Byte Low Byte EPSON S1D13806 SERIES PROGRAMMING NOTES 2-61 AND EXAMPLES (X28B-G-003-01)
Page 262 = ((Sx MOD 16 + BitBLTWidth + 15) ÷ 16) × BitBLTHeight where: Sx is the X coordinate of the starting pixel in a word aligned monochrome bitmap. Monochrome Bitmap Byte 1 Byte 2 Sx = EPSON 2-62 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 263 Since only bit 0 flags the source phase, more efficient code would simply write the low byte of the SourceAddress into REG[104h] directly -- not needing to test for an odd/even address. Note that in 16 bpp color depths the Source address is guaranteed to be even. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-63 AND EXAMPLES (X28B-G-003-01)
Page 264 = (13 + 12 + 15) ÷ 16 = 40 ÷ 16 Therefore, the total WORDS the BitBLT engine expects to receive is calculated as follows. = nWordsOneLine × 18 nWords = 2 × 18 = 36 EPSON 2-64 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 265: Color Expand Bitblt With Transparency
All bits set to 0 that would be expanded to the background color in the Color Expand BitBLT are not expanded at all. Program REG[103h] to 09h instead of 08h. Programming the background color is not required. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-65 AND EXAMPLES (X28B-G-003-01)
Page 266: Solid Fill Bitblt
9. Once the BitBLT operation is finished, read one word from offset 0 in the BitBLT memory area to shutdown the BitBLT engine. Note: The order of register initialization is irrelevant as long as all relevant registers are programmed before the BitBLT is initiated. EPSON 2-66 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 267: Move Bitblt In A Positive Direction With Rop
Move BitBLT in Negative Direction with ROP. Destination Address greater than Source Address Destination Address less than Source Address Use Move BitBLT in Negative Direction Use Move BitBLT in Positive Direction Figure 10-1 Move BitBLT Usage EPSON S1D13806 SERIES PROGRAMMING NOTES 2-67 AND EXAMPLES (X28B-G-003-01)
Page 268 9. Once the BitBLT operation is finished, read one word from offset 0 in the BitBLT memory area to shutdown the BitBLT engine. Note: The order of register initialization is irrelevant as long as all relevant registers are programmed before the BitBLT is initiated. EPSON 2-68 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 269: Move Bitblt In Negative Direction With Rop
72h, and REG[104h] is set to D8h. Program the BitBLT Destination Start Address Registers. REG[10Ah] is set to 06h, REG[109h] is set to A4h, and REG[108h] is set to E2h. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-69 AND EXAMPLES (X28B-G-003-01)
Page 270 9. Once the BitBLT operation is finished, read one word from offset 0 in the BitBLT memory area to shutdown the BitBLT engine. Note: The order of register initialization is irrelevant as long as all relevant registers are programmed before the BitBLT is initiated. EPSON 2-70 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 271: Transparent Write Bitblt
Note: The BitBLT engine counts WORD writes in the BitBLT address space. This does not imply only 16-bit CPU instructions are acceptable. If a system is able to separate one DWORD write into two WORD writes, then 32-bit CPU instructions are acceptable. Otherwise, 16-bit CPU instructions are required. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-71 AND EXAMPLES (X28B-G-003-01)
Page 272 8. Program the BitBLT Memory Offset Registers to the ScreenStride in WORDS. = ScreenStride ÷ 2 BltMemoryOffset = 640 ÷ 2 = 320 = 140h REG[10Dh] is set to 01h and REG[10Ch] is set to 40h. EPSON 2-72 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 273 12. Once the BitBLT operation is finished, read one word from offset 0 in the BitBLT memory area to shutdown the BitBLT engine. Note: The order of register initialization is irrelevant as long as all relevant registers are programmed before the BitBLT is initiated. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-73 AND EXAMPLES (X28B-G-003-01)
Page 274: Transparent Move Bitblt In Positive Direction
2. Program the BitBLT Width Registers to 9 - 1. REG[111h] is set to 00h and REG[110h] is set to 08h. 3. Program the BitBLT Height Registers to 321 - 1. REG[113h] is set to 01h and REG[112h] is set to 40h (320 decimal). EPSON 2-74 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 275: Pattern Fill Bitblt With Rop
(the pattern start phase). This allows seamless redrawing of any part of the screen using the pattern fill. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-75 AND EXAMPLES (X28B-G-003-01)
Page 276 6. Program the BitBLT ROP Code Register to select Destination = Source. REG[102h] is set to 0Ch. 7. Program the BitBLT Color Format Select bit for 8 bpp operations. REG[101h] is set to 00h. EPSON 2-76 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 277: Pattern Fill Bitblt With Transparency
BitBLT engine also needs to know which pixel from the pattern is the first pixel in the destination rectangle (the pattern start phase). This allows seamless redrawing of any part of the screen using the pattern fill. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-77 AND EXAMPLES (X28B-G-003-01)
Page 278 4. Program the BitBLT Height Registers to 250-1. REG[113h] is set to 00h, and REG[112h] is set to F9h (249 decimal). 5. Program the BitBLT Operation Register to select the Pattern Fill BitBLT with Transparency. REG[103h] is set to 07h. EPSON 2-78 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 279 10. Once the BitBLT operation is finished, read one word from offset 0 in the BitBLT memory area to shutdown the BitBLT engine. Note: The order of register initialization is irrelevant as long as all relevant registers are programmed before the BitBLT is initiated. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-79 AND EXAMPLES (X28B-G-003-01)
Page 280: Move Bitblt With Color Expansion
65h, and REG[108h] is set to 90h. Program the BitBLT Source Start Address Registers. REG[106h] is set to 10h, REG[105h] is set to 00h, and REG[104h] is set to 00h. EPSON 2-80 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 281: Transparent Move Bitblt With Color Expansion
The Transparent Move BitBLT with Color Expansion is virtually identical to the Move BitBLT with Color Expansion. The background color is ignored and bits in the monochrome source bitmap set to 0 are not color expanded. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-81 AND EXAMPLES (X28B-G-003-01)
Page 282: Read Bitblt
ScreenStride = DisplayWidthInPixels × BytesPerPixels = 640 for 8 bpp Program the BitBLT Source Start Address Registers. REG[106h] is set to 00h, REG[105h] is set to 5Fh, and REG[104h] is set to 19h. EPSON 2-82 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 283 Destination Linear Select = 0, BitBLT Source Linear Select = 0). Start the BitBLT operation and wait for the BitBLT engine to start. REG[100h] is set to 80h, then wait until REG[100h] bit 7 returns a 1. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-83 AND EXAMPLES (X28B-G-003-01)
Page 284: S1D13806 Bitblt Synchronization
0. 3. Once the BitBLT operation is finished, read one word from offset 0 in the BitBLT memory area to shutdown the BitBLT engine. 4. Continue the program. EPSON 2-84 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 285: S1D13806 Bitblt Known Limitations
BitBLT Width must be > 1 for 16 bpp color depths and > 2 for 8 bpp. • One word must be read from the BitBLT area between each BitBLT operation. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-85 AND EXAMPLES (X28B-G-003-01)
Page 286: Crt/Tv Considerations
DAC. This would normally result in very bright colors on the display, but if IREF is reduced at the same time the display will remain at its intended brightness and power con- sumption is reduced. EPSON 2-86 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 287: Examples
3. Enable the CRT. REG[1FCh] is set to 1. Sample code demonstrating how to enable the CRT display is provided in the file 56_CRT.c. This file is available on the internet at www.eea.epson.com. 11.2 TV Considerations TV timings are based on either the NTSC or PAL specifications. The TV display can be output in either composite video or S-video format.
Page 288: Tv Filters
The Luminance Filter may improve the TV picture quality when in composite video format. For further information on the TV filters, see the “S1D13806 Hardware Functional Specification,” document number X28B-A-001-xx. EPSON 2-88 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 289: Examples
(REG[1E0h] bit 0 = 0). Note: Not all combinations of panel and CRT/TV display resolutions are possible. For further information, see the “S1D13806 Hardware Functional Specification,” document number X28B-A-001-xx. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-89 AND EXAMPLES (X28B-G-003-01)
Page 290: Media Plug
Winnov. Cus- tomers intending to use the MediaPlug interface in their design should contact Epson Electronics America to obtain the latest S1D13806 MediaPlug drivers for testing purposes.
Page 291: Considerations
Register (REG[01Ch]) to select a clock source that is suitable, or program the clock divide bits to obtain a frequency within the correct range. If the S5U13806B00C evaluation board is used, the clock chip should be programmed to support a valid clock for the MediaPlug interface. EPSON S1D13806 SERIES PROGRAMMING NOTES 2-91 AND EXAMPLES (X28B-G-003-01)
Page 292: Identifying The S1D13806
3. The production version of the S1D13806 will return a value of 1Dh (00011101b). 4. The product code is 7 (000111b based on bits 7-2). 5. The revision code is 1 (01b based on bits 1-0). EPSON 2-92 S1D13806 SERIES PROGRAMMING NOTES AND EXAMPLES (X28B-G-003-01)
Page 294 S1D13806 Supported Evaluation Platforms................3-36 Installation ..........................3-36 Usage............................3-37 Display Surfaces ........................3-38 1386BMP Examples........................3-39 Comments..........................3-39 Program Messages ........................3-40 5 1386SWIVEL ........................3-42 S1D13806 Supported Evaluation Platforms................3-42 Installation ..........................3-42 Usage............................3-42 Example ............................ 3-43 EPSON S1D13806 SERIES UTILITIES...
Page 295 S1D13806 Supported Evaluation Platforms ................3-44 Installation..........................3-44 Usage ............................3-44 Filter Dialog Box ........................3-45 Filter Descriptions ........................3-46 6.5.1 Anti-flicker Filter ....................... 3-46 6.5.2 Chrominance Filter ....................3-46 6.5.3 Luminance Filter ...................... 3-46 Comments ..........................3-47 EPSON 3-ii S1D13806 SERIES UTILITIES...
Page 296 Figure 1-9 Save In Dialog Box......................3-13 Figure 6-1 Filter Dialog Box ......................... 3-45 List of Tables Table 2-1 Display Surfaces ........................ 3-17 Table 3-1 iCrtTv Selection ........................3-28 Table 4-1 Display Surfaces ........................ 3-38 EPSON S1D13806 SERIES UTILITIES 3-iii...
Page 297: 1386Cfg
Hardware Abstraction Layer (HAL) library. Note: It is possible to override recommended register settings and select incorrect panel timings using 1386CFG. Seiko Epson does not assume liability for any damage done to the display device as a re- sult of configuration errors.
Page 298: Usage
ASCII header file. Each utility must be configured separately. Note: 1386CFG is designed to work with utilities programmed using a given version of the HAL. If the con- figuration structure is of a different version, an error message is displayed. EPSON S1D13806 SERIES UTILITIES (X28B-B-001-01)
Page 299: General Tab
Note: PCI addresses are assigned by the system BIOS, and are not an option (grayed out in the example). For further information, see the “S1D13XX Windows 95/98/NT Device Driver Installation Guide,” doc- ument number X00A-E-003-xx. EPSON S1D13806 SERIES UTILITIES (X28B-B-001-01)
Page 300: Clocks Tab
“CRT/TV” tabs. Confirm all settings on these two tabs after manually changing any clock settings. Note: If the same source clock is selected for use by both CRT/TV and LCD panels, the available LCD pixel clock selections are limited due to the more stringent CRT/TV timings. EPSON S1D13806 SERIES UTILITIES (X28B-B-001-01)
Page 301 Selects the source for MCLK. MCLK Divide Selects the divide ratio for MCLK. Note: Under normal circumstances BCLK = BUSCLK. This option is only set for Toshiba/Philips when DCLKOUT is connected to the S1D13806 BUSCLK signal. EPSON S1D13806 SERIES UTILITIES (X28B-B-001-01)
Page 302: Panel Tab
This Panel Tab allows configuration of panel dimensions, type and timings. If the file PANELS.CFG is present in the same directory as 1386CFG.EXE, specific panels can be selected from a list of pre- defined panels. EPSON S1D13806 SERIES UTILITIES (X28B-B-001-01)
Page 303 Selects the desired pixel clock in KHz. TFT/FPLINE Selects the start position and pulse width in pixels. TFT/FPFRAME Selects the start position and pulse width in lines. Predefined Panels Selects from a list of predefined panels. EPSON S1D13806 SERIES UTILITIES (X28B-B-001-01)
Page 304: Crt/Tv Tab
Selects the format of the TV output (Composite or S-Video). Note: For CRT operations, 1386CFG supports VESA timings only. For TV operations, 1386CFG supports NTSC and PAL timings only. Overiding these register values may cause the CRT or TV to display in- correctly. EPSON S1D13806 SERIES UTILITIES (X28B-B-001-01)
Page 305: Defaults Tab
Note: 1386CFG doesn’t check for bandwidth limitations. It is possible to select modes which the S1D13806 doesn’t have enough bandwith to support. For a list of example modes, refer to the “S1D13806 Hard- ware Functional Specification,” document number X28B-A-001-xx. EPSON S1D13806 SERIES UTILITIES (X28B-B-001-01)
Page 306: Registers Tab
The manually entered values may be changed by 1386CFG if further configuration changes are made on the other tabs. In this case, the user is notified. Note: Manual changes to the registers may have unpredictable results if incorrect values are entered. EPSON 3-10 S1D13806 SERIES UTILITIES (X28B-B-001-01)
Page 307: Wince Tab
Selects the mode number used for the generation of the Windows CE header Mode Number files. Cursor Selects between Hardware Cursor, software cursor and no cursor support. Hardware Acceleration Selects whether 2D BitBlt hardware acceleration is used. EPSON S1D13806 SERIES UTILITIES (X28B-B-001-01) 3-11...
Page 308: Open File Dialog Box
.EXE file for Intel platforms, and from a specific S9 or ELF file for non-Intel platforms. The file must have been compiled using a valid version of the 13806 HAL library. EPSON 3-12 S1D13806 SERIES UTILITIES (X28B-B-001-01)
Page 309: Save In Dialog Box
PCI, MPC and IDP based programs at the same time for a new panel type, the physical addresses for each are retained. Checking “Preserve File Date and Time” saves the files without changing the date or time stamp of the file. EPSON S1D13806 SERIES UTILITIES (X28B-B-001-01) 3-13...
Page 310: Comments
(see document number X28B-A-001-xx) memory and LCD timings. If this is done, unpredictable results may occur. • To see the current configuration options in condensed form, use the “View File” option and select APPCFG.H. EPSON 3-14 S1D13806 SERIES UTILITIES (X28B-B-001-01)
Page 311: 1386Show
• MPC821ADS (Applications Development System) board, revision B, with a Motorola MPC821 processor. 2.2 Installation PC platform: Copy the file 1386show.exe to a directory specified in the path (e.g. PATH=C:\13806). Embedded platform: Download the program 1386show to the system. EPSON S1D13806 SERIES UTILITIES (X28B-B-002-01) 3-15...
Page 312: Usage
Enables SwivelView 90° mode, clockwise hardware rotation of LCD image by 90 degrees. /r180 Enables SwivelView 180° mode, clockwise hardware rotation of LCD image by 180 degrees. /r270 Enables SwivelView 270° mode, clockwise hardware rotation of LCD image by 270 degrees. EPSON 3-16 S1D13806 SERIES UTILITIES (X28B-B-002-01)
Page 313: Display Surfaces
1.25MB display buffer. Note: Only Surfaces 5 and 6 support SwivelView as it requires a separate memory block for the LCD. Sur- faces 3 and 4 use the same memory block for both displays. EPSON S1D13806 SERIES UTILITIES (X28B-B-002-01) 3-17...
Page 314: 1386Show Examples
Note: If a monochrome LCD panel is used, the image is formed using only the green component of the Look-Up Table for 4 and 8 bpp color depths. For 16 bpp color depths the green component of the pixel value is used. EPSON 3-18 S1D13806 SERIES UTILITIES (X28B-B-002-01)
Page 315 Once all screens are shown the program exits. To exit the pro- gram immediately press the Esc key. The “/s” switch can be used in combination with other command line switches. EPSON S1D13806 SERIES UTILITIES (X28B-B-002-01) 3-19...
Page 316: Using 1386Show For Testing
Note: If 1386SHOW is configured for a default display surface which includes LCD, the color pattern for the default LCD color depth is displayed as well as the specified CRT/TV color depth. EPSON 3-20 S1D13806 SERIES UTILITIES (X28B-B-002-01)
Page 317: Comments
• SwivelView 90° and 270° modes (/r90, /r270) are available only for color depths of 8 and 16 bpp. • SwivelView 180° mode (/r180) is available for color depths of 4, 8, and 16 bpp. EPSON S1D13806 SERIES UTILITIES (X28B-B-002-01) 3-21...
Page 318: Program Messages
A color depth of 4 bpp is not supported in SwivelView 90° or SwivelView 270° modes. ERROR: Do not select 4 bpp LCD in SwivelView 90° or SwivelView 270°. The “bl=” option selected a color depth not supported with SwivelView enabled. EPSON 3-22 S1D13806 SERIES UTILITIES (X28B-B-002-01)
Page 319 ERROR: Not enough memory for virtual display. Insufficient memory for the lower resolution display to create a virtual display of the image shown on the higher resolution display. ERROR: Could not initialize virtual display. Could not set up virtual image. EPSON S1D13806 SERIES UTILITIES (X28B-B-002-01) 3-23...
Page 320: 1386Play
• MC68030IDP (Integrated Development Platform) board, revision 3.0, with a Motorola MC68030 processor. • SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. • MPC821ADS (Applications Development System) board, revision B, with a Motorola MPC821 processor. EPSON 3-24 S1D13806 SERIES UTILITIES (X28B-B-003-01)
Page 321: Installation
3.3 Usage PC platform At the prompt, type: 1386play [/?] Where: displays program version information. Embedded platform Execute 1386play and at the prompt, type the command line argument /?. Where: displays program version information. EPSON S1D13806 SERIES UTILITIES (X28B-B-003-01) 3-25...
Page 322: Commands
Data to be written (hex). Data can be a list of bytes that will be repeated for the duration of the fill. To use decimal values, attach a “t” suffix to the value. (e.g. 100t is 100 decimal) EPSON 3-26 S1D13806 SERIES UTILITIES (X28B-B-003-01)
Page 323 Setting the number of lines to 0 will disable the halt function and allow the data to continue displaying until all data has been shown. Where: lines Number of lines that will be shown before halting the displayed data (decimal value). EPSON S1D13806 SERIES UTILITIES (X28B-B-003-01) 3-27...
Page 324 Initializes for the CRT display. Initializes for the TV display. II {LCD|CRT|TV} Initializes the Ink Layer for a given display type. Where: Initializes for the LCD display. Initializes for the CRT display. Initializes for the TV display. EPSON 3-28 S1D13806 SERIES UTILITIES (X28B-B-003-01)
Page 325 Displays help information for the M and MC commands. Sets the color depth of the LCD display. Sets the color depth of the CRT display. Sets the color depth of the TV display. Color depth to be set (4/8/16 bpp). EPSON S1D13806 SERIES UTILITIES (X28B-B-003-01) 3-29...
Page 326 To use decimal values, attach a “t” suffix to the value (e.g. 100t is 100 decimal). To use binary values attach a “‘b” suffix to the value (e.g. 0111’b). EPSON 3-30 S1D13806 SERIES UTILITIES (X28B-B-003-01)
Page 327 To use decimal values, attach a “t” suffix to the value (e.g. 100t is 100 decimal). To use binary values attach a “‘b” suffix to the value (e.g. 0111’b). EPSON S1D13806 SERIES UTILITIES (X28B-B-003-01) 3-31...
Page 328: 1386Play Example
8. Type f 0 1fffff aa to fill 2M bytes of the display buffer with AAh. 9. Type r 0 100 to read the first 100h bytes of the display buffer. 10. Type q to exit the program. EPSON 3-32 S1D13806 SERIES UTILITIES (X28B-B-003-01)
Page 329: Scripting
•10 = 10h = 16 decimal. •10t = 10 decimal. •010’b = 2 decimal. • Redirecting commands from a script file (PC platform) allows those commands to be executed as if entered by a user. EPSON S1D13806 SERIES UTILITIES (X28B-B-003-01) 3-33...
Page 330: Program Messages
ERROR: Invalid iFreq value. The CLKI and/or CLKI2 commands were used with an invalid iFreq value. To display a list of iFreq values, type CLKI ? or CLKI2 ?. EPSON 3-34 S1D13806 SERIES UTILITIES (X28B-B-003-01)
Page 331 WARNING: FEATCLK cannot be multiplexed to CLKI. Clock synthesizer programmed instead. In 1386PLAY, the CLKI command was used to select the FEATCLK frequency. Since the FEATCLK can only be multiplexed to CLKI2, the clock synthesizer is programmed instead. EPSON S1D13806 SERIES UTILITIES (X28B-B-003-01) 3-35...
Page 332: 1386Bmp
• PC with an Intel 80 × 86 processor running Windows 9x/NT. Note: The 1386BMP source code may be modified by the OEM to support other evaluation platforms. 4.2 Installation Copy the file 1386bmp.exe to a directory in the path (e.g. PATH=C:\S1D13806). EPSON 3-36 S1D13806 SERIES UTILITIES (X28B-B-004-01)
Page 333: Usage
Enables SwivelView 270° mode, clockwise hardware rotation of LCD image by 270 degrees. Verbose mode (provides information about the displayed image). Displays the help message. Note: 1386BMP displays the bmpfile image(s) and returns to the prompt. EPSON S1D13806 SERIES UTILITIES (X28B-B-004-01) 3-37...
Page 334: Display Surfaces
1.25MB display buffer. Note: Only Surfaces 5 and 6 support SwivelView as it requires a separate memory block for the LCD. Sur- faces 3 and 4 use the same memory block for both displays. EPSON 3-38 S1D13806 SERIES UTILITIES (X28B-B-004-01)
Page 335: 1386Bmp Examples
Therefore, only a portion of the image is viewable. To show a com- plete image on the smaller display, specify two separate bmpfiles with resolutions matching the intended display device. EPSON S1D13806 SERIES UTILITIES (X28B-B-004-01) 3-39...
Page 336: Program Messages
There was insufficient display buffer for the given configuration. Memory requirements depend on: • the display resolution(s). • the bit-per-pixel depth(s). • whether a Dual Panel Buffer is required. • the number of displays active (LCD or LCD and CRT/TV). EPSON 3-40 S1D13806 SERIES UTILITIES (X28B-B-004-01)
Page 337 The correct frequency was not found in the HAL table used to program the clock synthesizer. An external oscillator may be in use. This warning message will not stop the program. WARNING: CRT/TV only available in LANDSCAPE mode. SwivelView is only available on LCD only configurations. EPSON S1D13806 SERIES UTILITIES (X28B-B-004-01) 3-41...
Page 338: 1386Swivel
Copy the file 1386swivel.exe to a directory in the path. If desired, create a shortcut on the Windows 9x/NT desktop to the file 1386swivel.exe. 5.3 Usage At the Windows DOS Prompt, type: 1386swivel Note: Pressing the ESC key exits the program. EPSON 3-42 S1D13806 SERIES UTILITIES (X28B-B-006-01)
Page 339: Example
• 1386SWIVEL supports 8 and 16 bpp color depths only. • For further information on SwivelView™, refer to the “S1D13806 Hardware Functional Specifi- cation” (document number X28B-A-001-xx) and the “S1D13806 Programming Notes and Exam- ples” (document number X28B-G-003-xx). EPSON S1D13806 SERIES UTILITIES (X28B-B-006-01) 3-43...
Page 340: 1386Filt
Copy the file 1386filt.exe to a directory in the path. If desired, create a shortcut on the Windows 9x/ NT desktop to the file 1386filt.exe. 6.3 Usage In Windows 9x/NT, double-click the following icon: Or, at the Windows DOS Prompt, type 1386filt. EPSON 3-44 S1D13806 SERIES UTILITIES (X28B-B-005-01)
Page 341: Filter Dialog Box
When the box is unchecked the filter is disabled. In the example below: • the flicker filter is enabled. • the chrominance filter is enabled. • the luminance filter is enabled. Figure 6-1 Filter Dialog Box EPSON S1D13806 SERIES UTILITIES (X28B-B-005-01) 3-45...
Page 342: Filter Descriptions
The luminance filter adjusts the brightness of the TV by limiting the bandwidth of the luminance signal (reducing cross-chrominance distortion). This reduces the “rainbow-like” colors at bound- aries between sharp luminance transitions. This filter is intended for use with composite video out- put. EPSON 3-46 S1D13806 SERIES UTILITIES (X28B-B-005-01)
Page 343 • The chrominance and luminance filters are intended for use with composite output. • For information on manually enabling/disabling the TV filters, refer to the “S1D13806 Hardware Functional Specification” (document number X28B-A-001-xx) and the “S1D13806 Programming Notes and Examples” (document number X28B-G-003-xx). EPSON S1D13806 SERIES UTILITIES (X28B-B-005-01) 3-47...
Page 344 6: 1386FILT THIS PAGE IS BLANK. EPSON 3-48 S1D13806 SERIES UTILITIES (X28B-B-005-01)
Page 346 NTERFACE MediaPlug Interface Pin Mapping ..................... 4-16 ................4-17 LOCK YNTHESIZER AND LOCK PTIONS Clock Programming........................4-17 .........................4-18 EFERENCES 10 P ...........................4-19 ARTS 11 S ......................4-22 CHEMATIC IAGRAMS 12 PCB L ........................4-30 AYOUT EPSON S5U13806B00C REV 1.0 EVALUATION BOARD USER’S MANUAL...
Page 347 External CPU Host Connector (H2) Pinout ................ 4-11 Table 5-1 LCD Signal Connector (H3) ....................4-12 Table 6-1 CRT/TV Connectors Pin Mapping..................4-15 Table 7-1 MediaPlug Connector (J1) Pin Mapping ................4-16 Table 10-1 Parts List ..........................4-19 EPSON 4-ii S5U13806B00C REV 1.0 EVALUATION BOARD USER’S MANUAL...
Page 348: Introduction
S5U13806B00C is designed as an evaluation platform for the S1D13806 Embedded Memory Dis- play Controller chip. This user manual will be updated as appropriate. Please check the latest revision of this document before beginning any development. EPSON S5U13806B00C REV 1.0 EVALUATION BOARD USER’S MANUAL (X28B-G-004-03)
Page 349: Features
320 × 240 × 256 color at up to 30fps with on- • WINNOV VideumCam chip MediaPlug interface. • Programmable Clock synthesizer for maximum clock flexibility (CLKI and CLKI2). • Software initiated Power Save Mode. EPSON S5U13806B00C REV 1.0 EVALUATION BOARD USER’S MANUAL (X28B-G-004-03)
Page 350: Installation And Configuration
In order to configure the S1D13806 for multiple host bus interfaces an eight-position DIP switch (S1) is required. The following figure shows the location of DIP switch S1 on the S5U13806B00C. DIP Switch - S1 Figure 3-1 Configuration DIP Switch (S1) Location EPSON S5U13806B00C REV 1.0 EVALUATION BOARD USER’S MANUAL (X28B-G-004-03)
Page 351 MediaPlug output pin VMPEPWR and disables MediaPlug register access enables MediaPlug Register access — S1-8 nCONFIG Disable FPGA for non-PCI host Enable FPGA for PCI host = Required configuration when used in a PCI environment EPSON S5U13806B00C REV 1.0 EVALUATION BOARD USER’S MANUAL (X28B-G-004-03)
Page 352: Configuration Jumpers
X28B-A-001-xx for details. Note: For LCD only, JP1 should be left at the default setting (position 2-3). IREF is not required for LCD dis- plays. 4.6mA 9.2mA Figure 3-2 Configuration Jumper (JP1) Location EPSON S5U13806B00C REV 1.0 EVALUATION BOARD USER’S MANUAL (X28B-G-004-03)
Page 353 (Active High) (Active Low) Figure 3-4 Configuration Jumper (JP3) Location For further information on the LCD bias power supplies, refer to Section 5.5, “LCD Power Sequenc- ing” on page 14 for details. EPSON S5U13806B00C REV 1.0 EVALUATION BOARD USER’S MANUAL (X28B-G-004-03)
Page 354: Cpu Host Interface
00 1000h to 00 1FFFh 10 0000h to 1F FFFFh BitBlt data registers (1M byte) 10 0000h to 1F FFFFh 20 0000h to 33 FFFFh Display Buffer (1.25M byte) 00 0000h to 13 FFFFh EPSON S5U13806B00C REV 1.0 EVALUATION BOARD USER’S MANUAL (X28B-G-004-03)
Page 355: On-Board Pci Configuration Registers
Bits 31 to 22; other bits are zero. Position of 4M byte reserved window 4.1.2 Utility Software All utility software for the S5U13806B00C evaluation board is fully PCI compliant and handles the PCI configuration registers automatically. EPSON S5U13806B00C REV 1.0 EVALUATION BOARD USER’S MANUAL (X28B-G-004-03)
Page 356: Non-Pci Host Interface Support
Note: Pull-up resistors are not provided on the S5U13806B00C. However, these pins are not used in their corresponding CPU interface mode and systems are responsible for connecting them to V using external pull-up resistors. EPSON S5U13806B00C REV 1.0 EVALUATION BOARD USER’S MANUAL (X28B-G-004-03)
Page 357: External Cpu Host Connector Pin Mapping
Connected to WE0# of the S1D13806 Connected to WAIT# of the S1D13806 Connected to CS# of the S1D13806 Connected to MR# of the S1D13806 Connected to WE1# of the S1D13806 Not connected EPSON 4-10 S5U13806B00C REV 1.0 EVALUATION BOARD USER’S MANUAL (X28B-G-004-03)
Page 358 Connected to RD/WR# of the S1D13806 Connected to BS# of the S1D13806 Connected to BUSCLK of the S1D13806 Connected to RD# of the S1D13806 Connected to A20 of the S1D13806 Not connected EPSON S5U13806B00C REV 1.0 EVALUATION BOARD 4-11 USER’S MANUAL (X28B-G-004-03)
Page 359: Lcd Interface
GPIO11 Note: 1. The polarity of GPIO11 sent to pin 40 can be inverted using jumper JP3. However, JP3 does not affect the polarity of the signals controlling the LCD bias power supplies. EPSON 4-12 S5U13806B00C REV 1.0 EVALUATION BOARD...
Page 360: Voltage Translation Buffers
For further information on controlling the LCD bias voltage, refer to Section 5.5, “LCD Power Sequencing” on page 14. Note: Before connecting the panel. set the potentiometer according to the panel’s specific voltage re- quirements. EPSON S5U13806B00C REV 1.0 EVALUATION BOARD 4-13 USER’S MANUAL (X28B-G-004-03)
Page 361: Lcd Power Sequencing
LCD panel power-on/power-off requirements. When connecting the S5U13806B00C to other platforms, ensure that the software is designed to handle the LCD power sequencing for the panel under test. EPSON 4-14 S5U13806B00C REV 1.0 EVALUATION BOARD...
Page 362: Crt/Tv Interface
Manual,” document number X28B-B-001-xx. Note: When this option is selected, S5U13806B00C jumper JP1 (I for DAC) must be set to position 1-2. For further information, see Section 3.2, “Configuration Jumpers” on page 5. EPSON S5U13806B00C REV 1.0 EVALUATION BOARD 4-15 USER’S MANUAL (X28B-G-004-03)
Page 363: Media Plug Interface ( For Winnov Videum ® Cam )
Note: 1. When the MediaPlug interface is enabled using S1-7 (CONF7), GPIO12 is configured as the Medi- aPlug output pin VMPEPWR and cannot be controlled by REG[005h] and REG[009h]. It must be controlled using the MediaPlug LCMD register (REG[1000h] bit 1). EPSON 4-16 S5U13806B00C REV 1.0 EVALUATION BOARD...
Page 364: Clock Synthesizer And Clock Options
CRT/TV PCLK to use the same clock input (CLKI or CLKI2).Then use the S1D13806 internal clock divides (LCD PCLK Divide REG[014h], CRT/TV PCLK Divide REG[018h]) to obtain the lower frequencies. EPSON S5U13806B00C REV 1.0 EVALUATION BOARD 4-17 USER’S MANUAL (X28B-G-004-03)
Page 365: References
9: REFERENCES EFERENCES • SEIKO EPSON CORP., “S1D13806 Hardware Functional Specification,” Document Number X28B-A-001-xx. • SEIKO EPSON CORP., “S1D13806 Programming Notes and Examples,” Document Number X28B-G-003-xx. • Cypress Semiconductor Corporation, ICD2061A Data Sheet. EPSON 4-18 S5U13806B00C REV 1.0 EVALUATION BOARD...
Page 366: Parts List
Do not populate--mask header" "1x2 .1"" pitch unshrouded HEADER 2 Do not populate--mask header" MediaPlug 9-pin Right Angle PCB Mini CUI Stack P/N:MD-90S or Digi- Conn. DIN Socket Key P/N:CP-2490-ND EPSON S5U13806B00C REV 1.0 EVALUATION BOARD 4-19 USER’S MANUAL (X28B-G-004-03)
Page 367 "1206 resistor, 5%" R53-55 150 1% "1206 resistor, 1%" R56-63 330K "1206 resistor, 5%" SW DIP-8 "DIP switch, 8-position" SW DIP-4 "DIP switch, 4-position" Do not populate--mask S1D13806F00A 144-pin QFP EPSON 4-20 S5U13806B00C REV 1.0 EVALUATION BOARD USER’S MANUAL (X28B-G-004-03)
Page 368 "Place at JP1: 1-2, JP2: 1-2 and "(JP1,JP2,JP3)" Shunt jumpers" JP3: 1-2" Bracket PCI bracket "Screw, pan head, #4-40 x 1/4""-- Screw "Pan head, #4-40 x 1/4""" please assemble bracket onto board" EPSON S5U13806B00C REV 1.0 EVALUATION BOARD 4-21 USER’S MANUAL (X28B-G-004-03)
Page 369: Schematic Diagrams
11: SCHEMATIC DIAGRAMS 11 S CHEMATIC IAGRAMS Figure 11-1 S5U13806B00C Schematics (1 of 8) EPSON 4-22 S5U13806B00C REV 1.0 EVALUATION BOARD USER’S MANUAL (X28B-G-004-03)
Page 370 11: SCHEMATIC DIAGRAMS Figure 11-2 S5U13806B00C Schematics (2 of 8) EPSON S5U13806B00C REV 1.0 EVALUATION BOARD 4-23 USER’S MANUAL (X28B-G-004-03)
Page 371 11: SCHEMATIC DIAGRAMS Figure 11-3 S5U13806B00C Schematics (3 of 8) EPSON 4-24 S5U13806B00C REV 1.0 EVALUATION BOARD USER’S MANUAL (X28B-G-004-03)
Page 372 11: SCHEMATIC DIAGRAMS Figure 11-4 S5U13806B00C Schematics (4 of 8) EPSON S5U13806B00C REV 1.0 EVALUATION BOARD 4-25 USER’S MANUAL (X28B-G-004-03)
Page 373 11: SCHEMATIC DIAGRAMS Figure 11-5 S5U13806B00C Schematics (5 of 8) EPSON 4-26 S5U13806B00C REV 1.0 EVALUATION BOARD USER’S MANUAL (X28B-G-004-03)
Page 374 11: SCHEMATIC DIAGRAMS Figure 11-6 S5U13806B00C Schematics (6 of 8) EPSON S5U13806B00C REV 1.0 EVALUATION BOARD 4-27 USER’S MANUAL (X28B-G-004-03)
Page 375 11: SCHEMATIC DIAGRAMS Figure 11-7 S5U13806B00C Schematics (7 of 8) EPSON 4-28 S5U13806B00C REV 1.0 EVALUATION BOARD USER’S MANUAL (X28B-G-004-03)
Page 376 11: SCHEMATIC DIAGRAMS Figure 11-8 S5U13806B00C Schematics (8 of 8) EPSON S5U13806B00C REV 1.0 EVALUATION BOARD 4-29 USER’S MANUAL (X28B-G-004-03)
Page 377: Pcb Layout
12: PCB LAYOUT 12 PCB L AYOUT Figure 12-1 PCB Layout EPSON 4-30 S5U13806B00C REV 1.0 EVALUATION BOARD USER’S MANUAL (X28B-G-004-03)
Page 379 Direct Connection to the Philips PR31500/PR31700 ..............5-37 4.4.1 Hardware Description....................5-37 4.4.2 S1D13806 Configuration..................5-39 4.4.3 Memory Mapping and Aliasing................. 5-40 System Design Using the IT8368E PC Card Buffer ..............5-41 4.5.1 Hardware Description....................5-41 EPSON S1D13806 SERIES APPLICATION NOTES...
Page 380 Host Bus Interface Signal Descriptions ..............5-66 StrongARM SA-1110 to S1D13806 Interface ................5-67 7.4.1 Hardware Description ....................5-67 7.4.2 S1D13806 Hardware Configuration ................. 5-68 7.4.3 Performance ......................5-68 7.4.4 StrongARM SA-1110 Register Configuration ............5-69 7.4.5 Register/Memory Mapping..................5-70 EPSON 5-ii S1D13806 SERIES APPLICATION NOTES...
Page 381 Host Bus Interface Pin Mapping..................5-65 Table 7-2 Summary of Power-On/Reset Options ................5-68 Table 7-3 RDFx Parameter Value versus CPU Maximum Frequency ..........5-69 Table 7-4 Register/Memory Mapping for Typical Implementation ............5-70 EPSON S1D13806 SERIES APPLICATION NOTES 5-iii...
Page 382: Nterfacing To The Pc Card Us
The designs described in this document are presented only as examples of how such interfaces might be implemented. This application note is updated as appropriate. Please check the latest revision of this document before beginning any development. EPSON S1D13806 SERIES APPLICATION NOTES (X28B-G-005-01)
Page 383: Interfacing To The Pc Card Bus
The WAIT# signal allows for asynchronous data transfers for memory, attribute, and IO access cycles. The RESET signal allows resetting of the card configuration by the reset line of the host CPU. EPSON S1D13806 SERIES APPLICATION NOTES (X28B-G-005-01)
Page 384: Memory Access Cycles
AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA Transfer Start Transfer Complete Figure 1-1 PC Card Read Cycle EPSON S1D13806 SERIES APPLICATION NOTES (X28B-G-005-01)
Page 385 Figure 1-2 illustrates a typical memory access write cycle on the PC Card bus. A[25:0] ADDRESS VALID REG# CE1# CE2# WAIT# D[15:0] Hi-Z Hi-Z DATA VALID Transfer Start Transfer Complete Figure 1-2 PC Card Write Cycle EPSON S1D13806 SERIES APPLICATION NOTES (X28B-G-005-01)
Page 386: S1D13806 Host Bus Interface
2. Although a clock is not directly supplied by the PC Card interface, one is required by the S1D13806 PC Card Host Bus Interface. For an example of how this can be accomplished see the discussion on BUSCLK in Section 1.3.2, “PC Card Host Bus Interface Signals” on page 6. EPSON S1D13806 SERIES APPLICATION NOTES (X28B-G-005-01)
Page 387: Pc Card Host Bus Interface Signals
• The Bus Start (BS#) signal is not used for the PC Card Host Bus Interface and should be tied high (connected to V • The RESET# (active low) input of the S1D13806 may be connected to the PC Card RESET (active high) using an inverter. EPSON S1D13806 SERIES APPLICATION NOTES (X28B-G-005-01)
Page 388: Pc Card To S1D13806 Interface
Since the bus clock frequency is not critical, nor does it have to be synchronous to the bus signals, it may be the same as CLKI. BS# (bus start) is not used and should be tied high (connected to V EPSON S1D13806 SERIES APPLICATION NOTES (X28B-G-005-01)
Page 389 When connecting the S1D13806 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13806 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states). Figure 1-3 Typical Implementation of PC Card to S1D13806 Interface EPSON S1D13806 SERIES APPLICATION NOTES (X28B-G-005-01)
Page 390: S1D13806 Hardware Configuration
Configure GPIO12 for normal use VMPEPWR = configuration for PC Card Host Bus Interface 1.4.3 Performance The S1D13806 PC Card Interface specification supports a BCLK up to 50MHz, and therefore can provide a high performance display solution. EPSON S1D13806 SERIES APPLICATION NOTES (X28B-G-005-01)
Page 391: Register/Memory Mapping
The PC Card socket provides 64M byte of address space. Since the PC Card address bits A[25:22] are ignored, the S1D13806 registers and display buffer are aliased within the allocated address space. If aliasing is undesirable, the address space must be fully decoded. EPSON 5-10 S1D13806 SERIES APPLICATION NOTES (X28B-G-005-01)
Page 392: Inec Vr4102/Vr4111 M
The designs described in this document are presented only as examples of how such interfaces might be implemented. This application note is updated as appropriate. Please check the latest revision of this document before beginning any development. EPSON S1D13806 SERIES 5-11 APPLICATION NOTES (28B-G-007-01)
Page 393: Interfacing To The Vr4102/Vr4111
LCD controller providing an easy interface to the CPU. A 16M byte block of memory is assigned for the LCD controller and its own chip select and ready signals are available. Word or byte accesses are controlled by the system high byte signal (SHB#). EPSON 5-12 S1D13806 SERIES APPLICATION NOTES (28B-G-007-01)
Page 394: Lcd Memory Access Cycles
The following figure illustrates typical NEC VR4102/VR4111 memory read and write cycles to the LCD controller interface. TCLK ADD[25:0] VALID SHB# LCDCS# WR#,RD# D[15:0] VALID (write) Hi-Z D[15:0] Hi-Z VALID (read) LCDRDY Figure 2-1 NEC VR4102/VR4111 Read/Write Cycles EPSON S1D13806 SERIES 5-13 APPLICATION NOTES (28B-G-007-01)
Page 395: S1D13806 Host Bus Interface
Table 2-1 Host Bus Interface Pin Mapping S1D13806 Pin Name NEC VR4102/VR4111 Pin Name AB[20:0] ADD[20:0] DB[15:0] DAT[15:0] WE1# SHB# M/R# ADD21 LCDCS# BUSCLK BUSCLK RD/WR# WE0# WAIT# LCDRDY RESET# connected to system reset EPSON 5-14 S1D13806 SERIES APPLICATION NOTES (28B-G-007-01)
Page 396: Host Bus Interface Signal Descriptions
The WAIT# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. • The BS# and RD/WR# signals are not used for the MIPS/ISA Host Bus Interface and should be tied high (connected to V EPSON S1D13806 SERIES 5-15 APPLICATION NOTES (28B-G-007-01)
Page 397: Vr4102/Vr4111 To S1D13806 Interface
Figure 2-2 Typical Implementation of NEC VR4102/VR4111 to S1D13806 Interface Note: For pin mapping, see Table 1-1, “PC Card Host Bus Interface Pin Mapping,” on page 5. EPSON 5-16 S1D13806 SERIES APPLICATION NOTES (28B-G-007-01)
Page 398: S1D13806 Hardware Configuration
The frequency of BUSCLK output is programmed from the state of pins TxD/CLKSEL2, RTS#/ CLKSEL1 and DTR#/CLKSEL0 during reset, and from the PMU (Power Management Unit) con- figuration registers of the NEC VR4102/VR4111. The S1D13806 works at any of the frequencies provided by the NEC VR4102/VR4111. EPSON S1D13806 SERIES 5-17 APPLICATION NOTES (28B-G-007-01)
Page 399: Register/Memory Mapping
The NEC VR4102/VR4111 provides 16M byte of address space. Since the NEC VR4102/VR4111 address bits ADD[25:22] are ignored, the S1D13806 registers and display buffer are aliased within the allocated address space. If aliasing is undesirable, the address space must be fully decoded. EPSON 5-18 S1D13806 SERIES APPLICATION NOTES (28B-G-007-01)
Page 400: Mmpc821 M
The designs described in this document are presented only as examples of how such interfaces might be implemented. This application note is updated as appropriate. Please check the latest revision of this document before beginning any development. EPSON S1D13806 SERIES 5-19 APPLICATION NOTES (X28B-G-008-01)
Page 401: Interfacing To The Mpc821
The bus can support both normal and burst cycles. Burst memory cycles are used to fill on-chip cache memory and for certain on-chip DMA operations. Normal cycles are used for all other data transfers. EPSON 5-20 S1D13806 SERIES APPLICATION NOTES (X28B-G-008-01)
Page 402: Normal (Non-Burst) Bus Transactions
Figure 3-1 “Power PC Memory Read Cycle” on page 21 illustrates a typical memory read cycle on the Power PC system bus. CLKOUT A[0:31] RD/WR TSIZ[0:1], AT[0:3] D[0:31] Sampled when TA low Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 3-1 Power PC Memory Read Cycle EPSON S1D13806 SERIES 5-21 APPLICATION NOTES (X28B-G-008-01)
Page 403: Burst Cycles
However, the exam- ple interfaces include circuitry to detect the assertion of BDIP and respond with BI if caching is accidently enabled for the S1D13806 address space. EPSON 5-22 S1D13806 SERIES APPLICATION NOTES (X28B-G-008-01)
Page 404: Memory Controller Module
• Up to 15 wait states may be inserted, or the peripheral can terminate the bus cycle itself by assert- ing TA (Transfer Acknowledge). • Any chip select may be programmed to assert BI (Burst Inhibit) automatically when its memory space is addressed by the processor core. EPSON S1D13806 SERIES 5-23 APPLICATION NOTES (X28B-G-008-01)
Page 405: User-Programmable Machine (Upm)
In this application note, the GPCM is used instead of the UPM, since the GPCM has enough flexibil- ity to accommodate the S1D13806 and it is desirable to leave the UPM free to handle other interfac- ing duties, such as EDO DRAM. EPSON 5-24 S1D13806 SERIES APPLICATION NOTES (X28B-G-008-01)
Page 406: S1D13806 Host Bus Interface
The following table shows the functions of each host bus interface signal. Table 3-1 PowerPC Host Bus Interface Pin Mapping S1D13806 Pin Names PowerPC AB[20:0] A[11:31] DB[15:0] D[0:15] WE1# M/R# PowerPC Internal Chip Select BUSCLK CLKOUT RD/WR# RD/WR TSIZ0 WE0# TSIZ1 WAIT# RESET# RESET# EPSON S1D13806 SERIES 5-25 APPLICATION NOTES (X28B-G-008-01)
Page 407: Powerpc Host Bus Interface Signals
S1D13806 internal registers and/or display buffer. The WAIT# line resolves these contentions by forcing the host to wait until resource arbitration is complete. • The Bus Start (BS#) signal connects to TS (the transfer start signal). EPSON 5-26 S1D13806 SERIES APPLICATION NOTES (X28B-G-008-01)
Page 408: Mpc821 To S1D13806 Interface
When connecting the S1D13806 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13806 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states). Figure 3-3 Typical Implementation of MPC821 to S1D13806 Interface EPSON S1D13806 SERIES 5-27 APPLICATION NOTES (X28B-G-008-01)
Page 409: Hardware Connections
AB14 P6-D23 AB13 P6-D22 AB12 P6-D19 AB11 P6-A19 AB10 P6-D28 P6-A28 P6-C27 P6-A26 P6-C26 P6-A25 P6-D26 P6-B25 P6-B19 P6-D17 P12-A9 DB15 P12-C9 DB14 P12-D9 DB13 P12-A8 DB12 P12-B8 DB11 P12-D8 DB10 P12-B7 P12-C7 EPSON 5-28 S1D13806 SERIES APPLICATION NOTES (X28B-G-008-01)
Page 410 P12-A5, P12-B5, P12-A6, P12-B6, P12-A7 Note: Note that the bit numbering of the Power PC bus signals is reversed. e.g. the most significant ad- dress bit is A0, the next is A1, A2, etc. EPSON S1D13806 SERIES 5-29 APPLICATION NOTES (X28B-G-008-01)
Page 411: S1D13806 Hardware Configuration
40 0000h to 40 01FFh Control Registers Decoded 40 1000h to 40 1FFFh MediaPlug Registers Decoded 50 0000h to 5F FFFFh BitBLT Registers Decoded 60 0000h to 73 FFFFh Display Buffer Decoded x = don’t care EPSON 5-30 S1D13806 SERIES APPLICATION NOTES (X28B-G-008-01)
Page 412: Mpc821 Chip Select Configuration
SETA below. • SETA = 1 – the S1D13806 generates an external transfer acknowledge using the WAIT# line. • TRLX = 0 – normal timing. • EHTR = 0 – normal timing. EPSON S1D13806 SERIES 5-31 APPLICATION NOTES (X28B-G-008-01)
Page 413: Test Software
S1D13806 mem space stbr1,DisableReg(r1); write 0 to disable register Loop lbzr0,RevCodeReg(r1); read revision code into r1 bLoop ; branch forever Note: MPC8BUG does not support comments or symbolic equates; these have been added for clarity. EPSON 5-32 S1D13806 SERIES APPLICATION NOTES (X28B-G-008-01)
Page 414: Introduction
The designs described in this document are presented only as examples of how such interfaces might be implemented. This application note is updated as appropriate. Please check the latest revision of this document before beginning any development. EPSON S1D13806 SERIES 5-33 APPLICATION NOTES (X28B-G-009-01)
Page 415: Interfacing To The Pr31500/Pr31700
• Direct connection to the PR31500/PR31700 (see Section 4.4, “Direct Connection to the Philips PR31500/PR31700” on page 37). • System design using the ITE IT8368E PC Card/GPIO buffer chip (see Section 4.5, “System Design Using the IT8368E PC Card Buffer” on page 41). EPSON 5-34 S1D13806 SERIES APPLICATION NOTES (X28B-G-009-01)
Page 416: S1D13806 Host Bus Interface
Table 4-1 PR31500/PR31700 Host Bus Interface Pin Mapping S1D13806 Pin Name Philips PR31500/PR31700 AB20 AB19 /CARDREG AB18 /CARDIORD AB17 /CARDIOWR AB[16:13] AB[12:0] A[12:0] DB[15:8] D[23:16] DB[7:0] D[31:24] WE1# /CARDxCSH M/R# BUSCLK DCLKOUT RD/WR# /CARDxCSL WE0# WAIT# /CARDxWAIT RESET# RESET# EPSON S1D13806 SERIES 5-35 APPLICATION NOTES (X28B-G-009-01)
Page 417: Pr31500/Pr31700 Host Bus Interface Signals
S1D13806 may occur asynchronously to the display update, it is possible that contention may occur in accessing the S1D13806 internal registers and/or display buffer. The WAIT# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. EPSON 5-36 S1D13806 SERIES APPLICATION NOTES (X28B-G-009-01)
Page 418: Direct Connection To The Philips Pr31500/Pr31700
DCLKOUT as clock source, and whether an external or internal clock divider is needed, should be based on the following criteria. • pixel and frame rates. • power budget. • part count. • maximum S1D13806 clock frequencies. The S1D13806 also has internal CLKI dividers providing additional flexibility. EPSON S1D13806 SERIES 5-37 APPLICATION NOTES (X28B-G-009-01)
Page 419 When connecting the S1D13806 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13806 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states). Figure 4-1 Typical Implementation of Direct Connection EPSON 5-38 S1D13806 SERIES APPLICATION NOTES (X28B-G-009-01)
Page 420: S1D13806 Configuration
CONF6 WAIT# is always driven WAIT# is floating if S1D13806 is not selected Configure GPIO12 as MediaPlug output pin CONF7 Configure GPIO12 for normal use VMPEPWR = configuration for PR31500/PR31700 Host Bus Interface EPSON S1D13806 SERIES 5-39 APPLICATION NOTES (X28B-G-009-01)
Page 421: Memory Mapping And Aliasing
4 times at 2M byte intervals S1D13806 display buffer, 0D80 0000h 8M byte aliased 4 times at 2M byte intervals 0E00 0000h 32M byte Card 2 IO or Attribute 6800 0000h 64M byte Card 2 Memory EPSON 5-40 S1D13806 SERIES APPLICATION NOTES (X28B-G-009-01)
Page 422: System Design Using The It8368E Pc Card Buffer
Philips PR31500/PR31700” on page 37. Following is a block diagram showing an implementation using the IT8368E PC Card buffer. PR31500/ S1D13806 PR31700 PC Card IT8368E Device PC Card IT8368E Device Figure 4-2 IT8368E Implementation Block Diagram EPSON S1D13806 SERIES 5-41 APPLICATION NOTES (X28B-G-009-01)
Page 423: It8368E Configuration
4: INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR 4.5.2 IT8368E Configuration The ITE IT8368E is specifically designed to support EPSON LCD/CRT controllers. Older EPSON Controllers not supporting a direct interface to the Philips processor can utilize the IT8368E MFIO pins to provide the necessary control signals, however when using the S1D13806 this is not neces- sary as the Direct Connection described in Section 4.4, “Direct Connection to the Philips PR31500/...
Page 424: Introduction
The designs described in this document are presented only as examples of how such interfaces might be implemented. This application note is updated as appropriate. Please check the latest revision of this document before beginning any development. EPSON S1D13806 SERIES 5-43 APPLICATION NOTES (X28B-G-010-01)
Page 425: Interfacing To The Tx3912
• Direct connection to the TX3912 (see Section 4.4, “Direct Connection to the Philips PR31500/ PR31700” on page 37). • System design using the ITE IT8368E PC Card/GPIO buffer chip (see Section 4.5, “System Design Using the IT8368E PC Card Buffer” on page 41). EPSON 5-44 S1D13806 SERIES APPLICATION NOTES (X28B-G-010-01)
Page 426: S1D13806 Host Bus Interface
Table 5-1 TX3912 Host Bus Interface Pin Mapping S1D13806 Toshiba TX3912 Pin Names AB20 AB19 CARDREG* AB18 CARDIORD* AB17 CARDIOWR* AB[16:13] AB[12:0] A[12:0] DB[15:8] D[23:16] DB[7:0] D[31:24] WE1# CARDxCSH* M/R# BUSCLK DCLKOUT RD/WR# CARDxCSL* WE0# WAIT# CARDxWAIT* RESET# PON* EPSON S1D13806 SERIES 5-45 APPLICATION NOTES (X28B-G-010-01)
Page 427: Tx3912 Host Bus Interface Signals
S1D13806 may occur asynchronously to the display update, it is possible that contention may occur in accessing the S1D13806 internal registers and/or display buffer. The WAIT# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. EPSON 5-46 S1D13806 SERIES APPLICATION NOTES (X28B-G-010-01)
Page 428: Direct Connection To The Toshiba Tx3912
DCLKOUT as clock source, and whether an external or internal clock divider is needed, should be based on the following criteria. • pixel and frame rates. • power budget. • part count. • maximum S1D13806 clock frequencies. The S1D13806 also has internal CLKI dividers providing additional flexibility. EPSON S1D13806 SERIES 5-47 APPLICATION NOTES (X28B-G-010-01)
Page 429 When connecting the S1D13806 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13806 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states). Figure 5-1 Typical Implementation of Direct Connection EPSON 5-48 S1D13806 SERIES APPLICATION NOTES (X28B-G-010-01)
Page 430: S1D13806 Configuration
CONF6 WAIT# is always driven WAIT# is floating if S1D13806 is not selected Configure GPIO12 as MediaPlug output pin CONF7 Configure GPIO12 for normal use VMPEPWR = configuration for TX3912 Host Bus Interface EPSON S1D13806 SERIES 5-49 APPLICATION NOTES (X28B-G-010-01)
Page 431: Memory Mapping And Aliasing
4 times at 2M byte intervals S1D13806 display buffer, 0D80 0000h 8M byte aliased 4 times at 2M byte intervals 0E00 0000h 32M byte Card 2 IO or Attribute 6800 0000h 64M byte Card 2 Memory EPSON 5-50 S1D13806 SERIES APPLICATION NOTES (X28B-G-010-01)
Page 432: System Design Using The It8368E Pc Card Buffer
Philips PR31500/PR31700” on page 37. Following is a block diagram showing an implementation using the IT8368E PC Card buffer. TX3912 S1D13806 PC Card IT8368E Device PC Card IT8368E Device Figure 5-2 IT8368E Implementation Block Diagram EPSON S1D13806 SERIES 5-51 APPLICATION NOTES (X28B-G-010-01)
Page 433: It8368E Configuration
5: INTERFACING TO THE TOSHIBA MIPS TX3912 PROCESSOR 5.5.2 IT8368E Configuration The ITE IT8368E is specifically designed to support EPSON LCD/CRT controllers. Older EPSON Controllers not supporting a direct interface to the Toshiba processor can utilize the IT8368E MFIO pins to provide the necessary control signals, however when using the S1D13806 this is not neces- sary as the Direct Connection described in Section 4.4, “Direct Connection to the Philips PR31500/...
Page 434: Introduction
The designs described in this document are presented only as examples of how such interfaces might be implemented. This application note is updated as appropriate. Please check the latest revision of this document before beginning any development. EPSON S1D13806 SERIES 5-53 APPLICATION NOTES (X28B-G-011-01)
Page 435: Interfacing To The Nec Vr4121
LCD controller providing an easy interface to the CPU. A 16M byte block of memory is assigned for the LCD controller and its own chip select and ready signals are avail- able. Word or byte accesses are controlled by the system high byte signal (SHB#). EPSON 5-54 S1D13806 SERIES APPLICATION NOTES (X28B-G-011-01)
Page 436 The following figure illustrates typical NEC VR4121 memory read and write cycles to the LCD controller interface. TCLK ADD[25:0] VALID SHB# LCDCS# WR#,RD# D[15:0] VALID (write) Hi-Z D[15:0] Hi-Z VALID (read) LCDRDY Figure 6-1 NEC VR4121 Read/Write Cycles EPSON S1D13806 SERIES 5-55 APPLICATION NOTES (X28B-G-011-01)
Page 437: S1D13806 Host Bus Interface
Table 6-1 Host Bus Interface Pin Mapping S1D13806 Pin Name NEC VR4121 Pin Name AB[20:0] ADD[20:0] DB[15:0] DAT[15:0] WE1# SHB# M/R# ADD21 LCDCS# BUSCLK BUSCLK RD/WR# WE0# WAIT# LCDRDY RESET# connected to system reset EPSON 5-56 S1D13806 SERIES APPLICATION NOTES (X28B-G-011-01)
Page 438: Host Bus Interface Signal Descriptions
The WAIT# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. • The BS# and RD/WR# signals are not used for the MIPS/ISA Host Bus Interface and should be tied high (connected to V EPSON S1D13806 SERIES 5-57 APPLICATION NOTES (X28B-G-011-01)
Page 439: Vr4121 To S1D13806 Interface
S1D13806 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states). Figure 6-2 NEC VR4121 to S1D13806 Configuration Schematic Note: For pin mapping see Table 1-1, “PC Card Host Bus Interface Pin Mapping,” on page 5. EPSON 5-58 S1D13806 SERIES APPLICATION NOTES (X28B-G-011-01)
Page 440: S1D13806 Configuration
The frequency of BUSCLK output is programmed from the state of pins TxD/CLKSEL2, RTS#/ CLKSEL1 and DTR#/CLKSEL0 during reset, and from the PMU (Power Management Unit) con- figuration registers of the NEC VR4121. The S1D13806 works at any of the frequencies provided by the NEC VR4121. EPSON S1D13806 SERIES 5-59 APPLICATION NOTES (X28B-G-011-01)
Page 441: Register/Memory Mapping
ADD[23:22] are ignored, the S1D13806 registers and display buffer are aliased within the allocated address space. If aliasing is undesirable, the address space must be fully decoded. Note: Address lines ADD[25:24] are set at 10b and never change while the LCD controller is being ad- dressed. EPSON 5-60 S1D13806 SERIES APPLICATION NOTES (X28B-G-011-01)
Page 442: Introduction
The designs described in this document are presented only as examples of how such interfaces might be implemented. This application note is updated as appropriate. Please check the latest revision of this document before beginning any development. EPSON S1D13806 SERIES 5-61 APPLICATION NOTES (X28B-G-012-01)
Page 443: Interfacing To The Strongarm Sa-1110 Bus
During a read cycle, the output enable signal (nOE) is driven low. A write cycle is specified by driv- ing nOE high and driving the write enable signal (nWE) low. The cycle can be lengthened by driv- ing RDY high for the time needed to complete the cycle. EPSON 5-62 S1D13806 SERIES APPLICATION NOTES (X28B-G-012-01)
Page 444 Figure 7-1 illustrates a typical variable-latency IO access read cycle on the SA-1110 bus. A[25:0] ADDRESS VALID nCS4 D[31:0] DATA VALID nCAS[3:0] Figure 7-1 SA-1110 Variable-Latency IO Read Cycle EPSON S1D13806 SERIES 5-63 APPLICATION NOTES (X28B-G-012-01)
Page 445 7: INTERFACING TO THE STRONGARM SA-1110 PROCESSOR Figure 1-2 illustrates a typical variable-latency IO access write cycle on the SA-1110 bus. A[25:0] ADDRESS VALID nCS4 D[31:0] DATA VALID nCAS[3:0] Figure 7-2 SA-1110 Variable-Latency IO Write Cycle EPSON 5-64 S1D13806 SERIES APPLICATION NOTES (X28B-G-012-01)
Page 446: S1D13806 Host Bus Interface
S1D13806 Pin Name SA-1110 AB[20:0] A[20:0] DB[15:0] D[15:0] WE1# nCAS1 M/R# nCS4 BUSCLK SDCLK2 RD/WR# nCAS0 WE0# WAIT# RESET# system RESET Note: 1. The bus signal A0 is not used by the S1D13806 internally. EPSON S1D13806 SERIES 5-65 APPLICATION NOTES (X28B-G-012-01)
Page 447: Host Bus Interface Signal Descriptions
• The Bus Start (BS#) signal is not used for this Host Bus Interface and should be tied high (con- nected to V • The RESET# (active low) input of the S1D13806 may be connected to the system RESET. EPSON 5-66 S1D13806 SERIES APPLICATION NOTES (X28B-G-012-01)
Page 448: Strongarm Sa-1110 To S1D13806 Interface
When connecting the S1D13806 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13806 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states). Figure 7-3 Typical Implementation of SA-1110 to S1D13806 Interface EPSON S1D13806 SERIES 5-67 APPLICATION NOTES (X28B-G-012-01)
Page 449: S1D13806 Hardware Configuration
• If SDCLK2 is used, bit 26 should be set to 1 to divide the CPU clock by 4. • If SDCLK1 is used, bit 22 should be set to 1 to divide the CPU clock by 4. EPSON 5-68 S1D13806 SERIES APPLICATION NOTES (X28B-G-012-01)
Page 450: Strongarm Sa-1110 Register Configuration
•If SDCLK2 is used, bit 26 should be set to 1 to divide the CPU clock by 4. •If SDCLK1 is used, bit 22 should be set to 1 to divide the CPU clock by 4. EPSON S1D13806 SERIES 5-69 APPLICATION NOTES (X28B-G-012-01)
Page 451: Register/Memory Mapping
Each chip select on the SA-1110 provides 64M byte of address space. Since the SA-1110 address bits A[25:22] are ignored, the S1D13806 registers and display buffer are aliased within the allocated address space. If aliasing is undesirable, the address space must be fully decoded. EPSON 5-70 S1D13806 SERIES APPLICATION NOTES (X28B-G-012-01)
Page 453 CONTENTS Contents Table of Contents 1 S1D13806 P ...................6-1 OWER ONSUMPTION Conditions ........................... 6-2 ..........................6-3 UMMARY EPSON S1D13806 SERIES POWER CONSUMPTION...
Page 454 CONTENTS List of Tables Table 1-1 S1D13806ES Total Power Consumption in mW..............6-2 EPSON 6-ii S1D13806 SERIES POWER CONSUMPTION...
Page 455 There is a power save mode in the S1D13806. The power consumption is affected by various system design variables. • Clock states during the power save mode: disabling the clocks during power save mode has sub- stantial power savings. EPSON S1D13806 SERIES POWER CONSUMPTION (X28B-G-006-01)
Page 456 • CLKI2 grounded when CRT/TV disabled • CLKI3 grounded • BUSCLK active • Self-Refresh DRAM 2. Conditions for power save mode with Clocks inactive: • CPU interface inactive • CLKI, CLKI2, CLKI3, BUSCLK stopped • Self-Refresh DRAM EPSON S1D13806 SERIES POWER CONSUMPTION (X28B-G-006-01)
Page 457 CPU Interface and Input Clock state. In a typical design environment, the S1D13806 can be configured to be an extremely power-effi- cient LCD/CRT/TV Controller with high performance and flexibility. EPSON S1D13806 SERIES POWER CONSUMPTION (X28B-G-006-01)
Page 458 2: SUMMARY THIS PAGE IS BLANK. EPSON S1D13806 SERIES POWER CONSUMPTION (X28B-G-006-01)
Page 460 CONTENTS Contents Table of Contents ® 1 WINDOWS CE DISPLAY DRIVERS ..................7-1 Program Requirements ....................... 7-1 Example Driver Builds......................... 7-2 Installation for CEPC Environment....................7-7 Comments........................... 7-8 ® EPSON S1D13806 SERIES WINDOWS CE DISPLAY DRIVER...
Page 461: Program Requirements
This document and the updated source code for the Windows CE drivers is updated as appropriate. Please check the latest revisions before beginning any development. 1.1 Program Requirements Video Controller : S1D13806 Display Type : LCD or CRT Windows Version : CE Version 2.0 and 2.11 ® EPSON S1D13806 SERIES WINDOWS CE DISPLAY DRIVER (X28B-E-001-01)
Page 462 Windows CE Platform Builder 2.11” on page 4. 5. Create a sub-directory named S1D13806 under \wince\platform\cepc\drivers\display. 6. Copy the source code to the S1D13806 subdirectory. 7. Add an entry for the S1D13806 in the file \wince\platform\cepc\drivers\display\dirs. EPSON ® S1D13806 SERIES WINDOWS CE DISPLAY DRIVER (X28B-E-001-01)
Page 463 CE DISPLAY DRIVERS 8. Edit the file PLATFORM.BIB (located in X:\wince\platform\cepc\files) to set the default display driver to the file EPSON.DLL. (EPSON.DLL will be created during the build in step 12) You may replace the following lines in PLATFORM.BIB: IF CEPC_DDI_VGA2BPP ddi.dll...
Page 464 1. Install Microsoft Windows NT v4.0. 2. Install Platform Builder 2.11 by running SETUP.EXE from compact disk #1. 3. Follow the steps below to create a “Build Epson for x86” shortcut which uses the current “Min- shell” project icon/shortcut on the Windows NT 4.0 desktop.
Page 465 8. If the current MODE0.H is not appropriate for your project, generate a new MODE0.H using the S1D13806 utility program 1386CFG.EXE. The file MODE0.H (located in X:\wince\plat- form\cepc\drivers\display\S1D13806) contains the register values required to set desired screen resolution, color depth (bpp), panel type, active display(LCD/CRT/TV), rotation, etc. ® EPSON S1D13806 SERIES WINDOWS CE DISPLAY DRIVER (X28B-E-001-01)
Page 466 11. Generate the proper building environment by double-clicking on the Epson project icon --”Build Epson for x86”. 12. Type BLDDEMO <ENTER> at the DOS prompt of the “Build Epson for x86” window to gener- ate a Windows CE image file (NK.BIN).
Page 467 Edit AUTOEXEC.BAT on the hard drive to contain the following lines. mode com1:9600,n,8,1 loadcepc /B:9600 /C:1 c:\wince\release\nk.bin d. Confirm that NK.BIN is located in c:\wince\release. e. Reboot the system from the hard drive. ® EPSON S1D13806 SERIES WINDOWS CE DISPLAY DRIVER (X28B-E-001-01)
Page 468 1.4 Comments • The display driver is CPU independent allowing use of the driver for other Windows CE Platform Builder v2.11 supported platforms. The file EPSON.CPP may require editing to return the correct value for PhysicalPortAddr, PhysicalVmemAddr, etc. • The sample code defaults to a 640 × 480 16-bit color dual passive LCD panel in SwivelView 0°...
Page 469 Telex: 65542 EPSCO HX Crystal Lake, IL 60014, U.S.A. Phone: +1-815-455-7630 Fax: +1-815-455-7633 Northeast EPSON TAIWAN TECHNOLOGY & TRADING LTD. 301 Edgewater Place, Suite 120 10F, No. 287, Nanking East Road, Sec. 3 Wakefield, MA 01880, U.S.A. Taipei Phone: +1-781-246-3600...
Page 470 In pursuit of “Saving” Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers’ dreams. Epson IS energy savings.
Page 471 S1D13806 Series Technicl Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ Issue July,2001 This manual was made with recycle papaer, Printed in Japan and printed using soy-based inks.