Epson S1D13504F00A Manuals

Manuals and User Guides for Epson S1D13504F00A. We have 1 Epson S1D13504F00A manual available for free PDF download: Technical Manual

Epson S1D13504F00A Technical Manual (274 pages)

Dot Matrix Graphics LCD Controller

Brand: Epson | Category: Video Card | Size: 1 MB

Evaluation Board
3
Hardware Functional Specification
4
Programming Notes and Examples
4
Application Notes
4
Table of Contents
6
Introduction
12
Scope
12
Overview Description
12
Features
13
Memory Interface
13
CPU Interface
13
Display Support
13
Display Modes
14
Clock Source
14
Miscellaneous
14
Package and Pin
14
Table 2-1 S1D13504 Series Package List
14
Typical System Implementation Diagrams
15
Figure 3-1 Typical System Diagram - SH-3 Bus, 1Mx16 FPM/EDO-DRAM
15
Figure 3-2 Typical System Diagram - MC68K Bus 1, 1Mx16 FPM/EDO-DRAM (16-Bit MC68000)
15
Figure 3-3 Typical System Diagram - MC68K Bus 2, 256Kx16 FPM/EDO-DRAM (32-Bit MC68030)
16
Figure 3-4 Typical System Diagram - Generic Bus, 1Mx16 FPM/EDO-DRAM
16
Block Description
17
Functional Block Diagram
17
Functional Block Descriptions
17
Host Interface
17
Memory Controller
17
Display FIFO
17
Look-Up Table
17
LCD Interface
17
Power Save
17
Figure 4-1 System Block Diagram Showing Datapaths
17
Pin out
18
Pinout Diagram for S1D13504F00A
18
Figure 5-1 Pinout Diagram of S1D13504F00A
18
Pinout Diagram for S1D13504F01A
19
Figure 5-2 Pinout Diagram of S1D13504F01A
19
Pinout Diagram for S1D13504F02A
20
Figure 5-3 Pinout Diagram of S1D13504F02A
20
Pin Description
21
Host Interface
21
Table 5-1 Host Interface Pin Descriptions
21
Memory Interface
23
Table 5-2 Memory Interface Pin Descriptions
23
LCD Interface
24
Clock Input
24
CRT and External RAMDAC Interface
24
Table 5-3 LCD Interface Pin Descriptions
24
Table 5-4 Clock Input Pin Description
24
Table 5-5 CRT and RAMDAC Interface Pin Descriptions
24
Miscellaneous
25
Table 5-6 Miscellaneous Pin Descriptions
25
Power Supply
26
Table 5-7 Power Supply Pin Descriptions
26
Summary of Configuration Options
27
Multiple Function Pin Mapping
27
Table 5-8 Summary of Power on / Reset Options
27
Table 5-9 Host Bus Interface Pin Mapping
27
Table 5-10 Memory Interface Pin Mapping
27
Table 5-11 LCD, CRT, RAMDAC Interface Pin Mapping
28
C. Characteristics
29
Table 6-1 Absolute Maximum Ratings
29
Table 6-2 Recommended Operating Conditions
29
C. Characteristics
30
CPU Interface Timing
31
Interface Timing
31
Figure 7-1 SH-3 Interface Timing
31
Table 7-1 SH-3 Interface Timing
31
Figure 7-2 SH-3 Write Bus Timing
32
Table 7-2 SH-3 Write Bus Timing
32
MC68K Bus 1 Interface Timing (E.g. MC68000)
33
Figure 7-3 MC68000 Bus 1 Interfacetiming
33
Table 7-3 MC68000 Bus 1 Interfacetiming
33
Figure 7-4 MC68000 Read Bus Timing
34
Table 7-4 MC68000 Read Bus Timing
34
MC68K Bus 2 Interface Timing (E.g. MC68030)
35
Figure 7-5 MC68030 Bus 2 Interface Timing
35
Table 7-5 MC68030 Bus 2 Interface Timing
35
Figure 7-6 MC68030 Read Bus Timing
36
Table 7-6 MC68030 Read Bus Timing
36
Generic MPU Interface Synchronous Timing
37
Figure 7-7 Generic MPU Interface Synchronous Timing
37
Table 7-7 Generic MPU Interface Synchronous Timing
37
Figure 7-8 Generic Write Bus Synchronous Timing
38
Table 7-8 Generic Write Bus Synchronous Timing
38
Generic MPU Interface Asynchronous Timing
39
Figure 7-9 Generic MPU Interface Asynchronous Timing
39
Table 7-9 Generic MPU Interface Asynchronous Timing
39
Figure 7-10 Generic Write Bus Asynchronous Timing
40
Table 7-10 Generic Write Bus Asynchronoud Timing
40
Clock Input Requirements
41
Figure 7-11 Clock Input Requirements
41
Table 7-11 Clock Input Requirements
41
Memory Interface Timing
42
EDO-DRAM Read Timing
42
Figure 7-12 EDO-DRAM Read Timing
42
Table 7-12 EDO DRAM Read Timing
42
EDO-DRAM Write Timing
43
Figure 7-13 EDO-DRAM Write Timing
43
Table 7-13 EDO DRAM Write Timing
43
EDO-DRAM Read-Write Timing
44
Figure 7-14 EDO-DRAM Read-Write Timing
44
EDO-DRAM cas before RAS Refresh Timing
45
EDO-DRAM Self-Refresh Timing
45
Figure 7-15 EDO-DRAM cas before RAS Refresh Timing
45
Figure 7-16 EDO-DRAM Self-Refresh Timing
45
FPM-DRAM Read Timing
46
Figure 7-17 FPM-DRAM Read Timing
46
FPM-DRAM Write Timing
47
Figure 7-18 FPM-DRAM Write Timing
47
FPM-DRAM Read-Write Timing
48
Figure 7-19 FPM-DRAM Read-Write Timing
48
FPM-DRAM CAS# before RAS# Refresh Timing
49
FPM-DRAM Self-Refresh Timing
49
Figure 7-20 FPM-DRAM CAS# before RAS# Refresh Timing
49
Figure 7-21 FPM-DRAM CBR Self-Refresh Timing
49
Display Interface
50
Power on / Reset Timing
50
Figure 7-22 LCD Panel Power on / Reset Timing
50
Suspend Timing
51
Figure 7-23 LCD Panel Suspend Timing
51
Single Monochrome 4-Bit Panel Timing
52
Figure 7-24 Single Monochrome 4-Bit Panel Timing
52
Figure 7-25 Single Monochrome 4-Bit Panel A.C. Timing
53
Single Monochrome 8-Bit Panel Timing
54
Figure 7-26 Single Monochrome 8-Bit Panel Timing
54
Figure 7-27 Single Monochrome 8-Bit Panel A.C. Timing
55
Single Color 4-Bit Panel Timing
56
Figure 7-28 Single Color 4-Bit Panel Timing
56
Figure 7-29 Single Color 4-Bit Panel A.C. Timing
57
Single Color 8-Bit Panel Timing (Format 1)
58
Figure 7-30 Single Color 8-Bit Panel Timing (Format 1)
58
Figure 7-31 Single Color 8-Bit Panel A.C. Timing (Format 1)
59
Single Color 8-Bit Panel Timing (Format 2)
60
Figure 7-32 Single Color 8-Bit Panel Timing (Format 2)
60
Figure 7-33 Single Color 8-Bit Panel A.C. Timing (Format 2)
61
Single Color 16-Bit Panel Timing
62
Figure 7-34 Single Color 16-Bit Panel Timing
62
Figure 7-35 Single Color 16-Bit Panel A.C. Timing
63
Dual Monochrome 8-Bit Panel Timing
64
Figure 7-36 Dual Monochrome 8-Bit Panel Timing
64
Figure 7-37 Dual Monochrome 8-Bit Panel A.C. Timing
65
Dual Color 8-Bit Panel Timing
66
Figure 7-38 Dual Color 8-Bit Panel Timing
66
Figure 7-39 Dual Color 8-Bit Panel A.C. Timing
67
Dual Color 16-Bit Panel Timing
68
Figure 7-40 Dual Color 16-Bit Panel Timing
68
16-Bit TFT Panel Timing
70
CRT Timing
72
External RAMDAC Read / Write Timing
74
Registers
75
Register Mapping
75
Register Descriptions
76
Revision Code Register
76
Memory Configuration Registers
76
Panel/Monitor Configuration Registers
77
Display Configuration Registers
81
Clock Configuration Register
85
Power Save Configuration Registers
86
Miscellaneous Registers
87
Look-Up Table Registers
94
External RAMDAC Control Registers
96
Display Buffer
97
Image Buffer
98
Half Frame Buffer
98
Display Configuration
99
Display Mode Data Format
99
Image Manipulation
101
Clocking
102
Maximum MCLK : PCLK Ratios
102
Frame Rate Calculation
103
Look -U P Table Architecture
105
Gray Shade Display Modes
105
Bit-Per-Pixel Mode
105
Bit-Per-Pixel Mode
106
Color Display Modes
106
Bit-Per-Pixel Color Mode
106
Bit-Per-Pixel Color Mode
109
Power Save Modes
110
Hardware Suspend
110
Software Suspend
110
Power Save Mode Function Summary
111
Pin States in Power Save Modes
111
Introduction
120
Programming the S1D13504 Registers
121
Registers Requiring Special Consideration
121
REG[01] Bit 0 - Memory Type
121
REG[22] Bits 7-2 - Performance Enhancement Register 0
121
REG[02] Bit 1 - Dual/Single Panel Type
121
REG[1B] Bit 0 - Half Frame Buffer Disable
121
REG[23] Display FIFO
121
Register Initialization
122
Initialization Sequence
122
Initialization Example
122
Re-Programming Registers
123
Disabling the Half Frame Buffer Sequence
124
Display Buffer Location
125
Display Buffer Organization
125
Memory Organization for One Bit-Per-Pixel (2 Colors/Gray Shades)
125
Memory Organization for Two Bit-Per-Pixel (4 Colors/Gray Shades)
125
Memory Organization for Four Bit-Per-Pixel (16 Colors/Gray Shades)
125
Memory Organization for Eight Bit-Per-Pixel (256 Colors)
126
Memory Organization for 15 Bit-Per-Pixel (32768 Colors)
126
Look-Up Table (LUT)
127
Look-Up Table Registers
127
Look-Up Table Organization
128
Advanced Techniques
132
Virtual Display
132
Registers
132
Examples
133
Panning and Scrolling
134
Registers
135
Examples
136
Split Screen
137
Registers
137
Examples
138
Lcd Power Sequencing and Power Save Modes
139
Introduction to LCD Power Sequencing
139
Introduction to Power Save Modes
139
Registers
139
Suspend Sequencing
140
Suspend Enable Sequence
140
LCD Enable/Disable Sequencing (REG[0D] Bit 0)
141
Crt Considerations
142
Introduction
142
CRT Only
142
Simultaneous Display
143
Identifying the S1D13504
145
Hardware Abstraction Layer (Hal)
146
Introduction
146
API for 13504HAL
146
Initialization
146
Screen Manipulation
148
Color Manipulation
152
Drawing
154
Register Manipulation
156
Miscellaneous
156
Sample Code
157
Introduction
157
Sample Code Using 13504HAL API
157
Sample Code Without Using 13504HAL API
158
Appendix Supported Panel Values
162
13504Cfg.exe Configuration Program
168
Program Requirements
168
Installation
168
Usage
169
Script Mode
169
Interactive Mode
170
13504CFG Menu Bar
170
Files Menu
171
View Menu
172
Device Menu
173
Help Menu
179
Comments
180
Sample Program Messages
180
13504Show Demonstration Program
181
13504Show D P
181
S1D13504 Supported Evaluation Platforms
181
Installation
181
Usage
181
Comments
182
Program Messages
182
13504Splt Display Utility
183
S1D13504 Supported Evaluation Platforms
183
Installation
183
Usage
183
13504SPLT Example
184
Comments
184
Program Messages
184
13504Virt Display Utility
185
S1D13504 Supported Evaluation Platforms
185
Installation
185
Usage
185
13504VIRT Example
186
Comments
186
Program Messages
186
13504Play Diagnostic Utility
187
S1D13504 Supported Evaluation Platforms
187
Installation
187
Usage
187
13504PLAY Example
189
Scripting
189
Comments
189
Program Messages
192
Installation
193
Usage
193
Introduction
199
Features
199
Installation and Configuration
200
Cpu/Bus Interface Connector Pinouts
202
Host Bus Interface Pin Mapping
204
Technical Description
205
ISA Bus Support
205
Non-ISA Bus Support
205
DRAM Support
205
Decode Logic
206
Clock Input Support
206
Monochrome LCD Panel Support
206
Color Passive LCD Panel Support
206
Color TFT LCD Panel Support
206
External CMOS RAMDAC Support
206
Core V DD Power Supply
207
Power Save Modes
207
Power Supply
207
Adjustable LCD Panel Negative Power Supply
207
Adjustable LCD Panel Positive Power Supply
207
Cpu/Bus Interface Header Strips
207
Schematic Notes
207
Parts List
208
Schematic Diagrams
209
Interfacing to the Philips Mips Pr31500/Pr31700 Processor
219
Introduction
219
General Description
219
Direct Connection to the Philips PR31500/PR31700
220
Hardware Description
220
Memory Mapping and Aliasing
221
S1D13504 Configuration
221
System Design Using the IT8368E PC Card Buffer
222
Hardware Description-Using One IT8368E
222
IT8368E Configuration
224
S1D13504 Configuration
225
Software
226
Interfacing to the Nec V R 4102 Tm Microprocessor
227
Introduction
227
General Description
227
Rtm
227
Hardware Description
228
Software
229
Interfacing to the Pc Card Bus
230
Nterfacing to the Pc Card Us
230
Introduction
230
Interfacing to the PC Card Bus
231
The PC Card System Bus
231
S1D13504 Host Bus Interface
233
Bus Interface Modes
233
Generic MPU Host Bus Interface
234
PC Card to S1D13504 Interface
235
Hardware Description
235
S1D13504 Hardware Configuration
236
PAL Equations
236
Register/Memory Mapping
237
Software
238
References
239
Documents
239
Document Sources
239
Interfacing to the Motorola Mpc821 Microprocessor
240
Introduction
240
Interfacing to the MPC821
241
The Mpc8Xx System Bus
241
Overview
241
Memory Controller Module
244
User-Programmable Machine (UPM)
244
S1D13504 Bus Interface
245
Bus Interface Modes
245
Generic Bus Interface Mode
246
MPC821/S1D13504 Interface
247
Hardware Connections
247
S1D13504 Hardware Configuration
249
MPC821 Chip Select Configuration
250
Test Software
251
References
252
Documents
252
Document Sources
252
Interfacing to the Motorola Mmcf5307 Microprocessor
254
Interfacing to the MCF5307
254
The MCF5307 System Bus
254
Overview
254
Normal (Non-Burst) Bus Transactions
254
Chip-Select Module
255
S1D13504 Bus Interface
256
Bus Interface Modes
256
Generic Bus Interface Mode
257
MCF5307 to S1D13504 Interface
258
Hardware Connections
258
S1D13504 Hardware Configuration
259
MCF5307 Chip Select Configuration
260
References
261
Documents
261
Document Sources
261
Interfacing to the Toshiba Mips Tx3912 Processor
262
Introduction
262
General Description
262
Direct Connection to the Toshiba TX3912
263
Hardware Description
263
Memory Mapping and Aliasing
264
S1D13504 Configuration
264
System Design Using the IT8368E PC Card Buffer
265
Hardware Description-Using One IT8368E
265
Hardware Description-Using Two It8368E's
266
IT8368E Configuration
267
Memory Mapping and Aliasing
267
S1D13504 Configuration
268
Software
269
Power Consumption
270
S1D13504 Power Consumption
270
Conditions
271

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Epson S1D13504F00A Technical Manual (274 pages)

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