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abaco systems PPC11A Manuals
Manuals and User Guides for abaco systems PPC11A. We have
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abaco systems PPC11A manual available for free PDF download: Hardware Reference Manual
abaco systems PPC11A Hardware Reference Manual (159 pages)
6U VME
Brand:
abaco systems
| Category:
Motherboard
| Size: 2.73 MB
Table of Contents
Document History
2
About this Manual
3
Further Information
3
Table of Contents
6
1 Unpacking
16
Box Contents Checklist
16
Identifying Your Board
16
Figure 1-1 Product Label (Packaging)
16
Figure 1-2 Product Label (Product)
16
Figure 1-3 Product Label (Conduction-Cooled Product)
17
2 Configuration
18
Link Configuration
18
Figure 2-1 Link Positions
18
Inspection
19
Configuration Link Descriptions
19
Boot Area Selection Link (P15 Pins 1 to 4)
19
Table 2-1 P15 Pins 1 to 4 Jumper Functions
19
NVRAM Write Enable Link (P15 Pins 5 and 6)
20
Flash Protection Unlock Link (P15 Pins 7 and 8)
20
Configuration Write Enable Link (P15 Pins 9 and 10)
20
Table 2-2 P15 Pins 5 and 6 Jumper Function
20
Table 2-3 P15 Pins 7 and 8 Jumper Function
20
Table 2-4 P15 Pins 9 and 10 Jumper Function
20
PMC1 & PMC2 5V VIO Selection Links (P15 Pins 13 to 16)
21
Reserved Links (P17 and P18)
21
Software Board Configuration
21
Table 2-5 P15 Pins 13 and 14 Jumper Functions
21
Table 2-6 P15 Pins 15 and 16 Jumper Functions
21
Mezzanine Installation
22
Figure 2-2 PMC/XMC Site Locations
22
3 Installation and Power Up/Reset
24
Power Supply Requirements
24
Board Installation Notes
24
Connecting to PPC11A
25
Rear Transition Module
25
Reset and Power-Up Sequence
25
4 Functional Description
26
Introduction
26
Figure 4-1 PPC11A General View
26
Figure 4-2 Block Diagram (T2081)
27
Figure 4-3 Block Diagram (T1042)
28
Features
29
Integrated Host Processor
30
Processor Features
30
Powerpc Processing Cores
30
Trust Architecture
30
Table 4-1 Processor Features
30
Table 4-2 Processor Frequencies
30
Memory Map
31
Reset Configuration Word
31
Processor Power Management
31
Local Bus
32
Table 4-3 Local Bus Chip Select Targets
32
Sdram
33
Capacity
33
Serial Presence Detect
33
NOR Flash
33
Table 4-4 SDRAM Configuration
33
Table 4-5 Flash Details
33
Boot Flash
34
Flash Sector Protection
34
Paged Flash Mode
34
User Flash
34
SPI Serial Recovery Flash
35
NAND Flash Solid State Drive
35
Nvsram
35
Functional Description (Continued)
35
VME Interface
36
Vmebus Compliance
36
Table 4-6 Vmebus Compliance
36
Vmebus Master Access
37
Vmebus Slave Access
37
Indivisible Cycles on VME
37
Vmebus Arbitration and Slot 1 Functions
37
Vmebus Master Block Transfers (DMA)
38
Vmebus Slave Block Transfers
38
Vmebus Interrupts
38
Vmebus Errors
38
Vmebus Retries
39
I/O
39
Ethernet
40
Table 4-7 Processor Network Interface Mapping
40
Table 4-8 ETH0/ETH1 Pin Mapping
40
Figure 4-4 Ethernet PHY Block Diagram
40
Serial Communication Ports
41
COM1 and COM2
41
Table 4-9 ETH2/ETH3 10/100/1000BASE-T Pin Mapping
41
Table 4-10 COM1/COM2 Signal Routing
41
Figure 4-5 RS422/485 Signal Definition
41
COM3 to COM6
42
Table 4-11 COM3 and COM4 Signal Routing
42
Host-To-BMM Serial Port
43
Usb
43
Table 4-12 COM5 Signal Routing
43
Table 4-13 COM6 Signal Routing
43
Table 4-14 USB0/USB1 Signal Routing
43
Sata
44
Gpio
44
Table 4-15 SATA Signal Routing
44
Table 4-16 GPIO Line Routing
45
Mil-Std-1553
46
Table 4-17 MIL-STD-1553 Routing
46
Graphics
47
Vga
47
DVI
47
Table 4-18 VGA Routing
47
Table 4-19 DVI Routing
47
Mezzanines
48
PMC/XMC Sites
48
Pmcs
48
Xmcs
49
I/O Routing
49
PMC/XMC Site 1 Configuration
49
Table 4-20 PMC/XMC Site 1 Signal Availability
50
PMC/XMC Site 2 Configuration
51
Table 4-21 PMC Site 2 (1:46) Signal Availability
51
Table 4-22 PMC Site 2 (47:64) Signal Availability
51
Pcie Infrastructure
52
Processor
52
Table 4-23 PCI and Pcie Bandwidths
52
Pcie Switches
53
Table 4-24 Pcie Switch 1 Connections
53
Table 4-25 Pcie Switch 1 Connections
53
I 2 C Buses
55
Main Bus
55
Table 4-26 I 2 C Main Bus Addresses
55
Figure 4-6 I 2 C Main Bus Structure
55
Sensor and Backplane Buses
56
Table 4-27 I 2 C Sensor Bus Addresses
56
Figure 4-7 I 2 C Sensor/Backplane Bus Structure
56
I 2 C Bus 3
57
I 2 C Reset
57
Processor Config EEPROM
57
Elapsed Time Indicator
57
Table 4-28 I 2 C Bus 3 Addresses
57
Figure 4-8 I 2 C Bus 3 Structure
57
DIP Switches
58
Table 4-29 PCA9560 Bit Meanings
58
Real-Time Clock
59
Temperature Sensor
59
Motion Sensor
59
Power Manager
59
Table 4-30 Power Manager Monitor Points
59
Timers
60
Watchdog Timer
60
AXIS Timer
61
Baseboard Management Microcontroller
61
Resets and Interrupts
62
Hard Reset
62
Table 4-31 External Interrupt Inputs to Processor
62
External Interrupt
63
Table 4-32 Processor PCI Intx and External IRQ Sharing
63
Fpga
64
Reset Configuration Word
64
Timings
64
Serial Presence Detect
64
AXIS Support
64
Jtag
65
Figure 4-9 JTAG Chains
65
Leds
66
Figure 4-10 LED Positions
66
DS10 and DS43 to DS45 (BIT)
67
Table 4-33 LED Functions
67
DS3 and DS4 (ETH0 Status)
68
DS46 and DS47 (ETH1 Status)
68
Conduction-Cooled Front Panel (Build Levels 4 and 5)
68
Figure 4-11 Conduction-Cooled Front Panel
68
Air-Cooled Front Panel (Build Levels 1 to 3)
69
Figure 4-12 0.8" Air-Cooled Front Panel
69
5 Control and Status Registers
70
Table 5-1 Control and Status Registers
70
Board ID Register (Offset 0X600)
72
Board Revision Register (Offset 0X601)
72
Master FPGA Revision Register (Offset 0X60B)
72
Slave FPGA Revision Register (Offset 0X60B)
73
Board ID String Register 1 (Offset 0X610) to Board ID String Register 11 (Offset 0X61A)
73
Reset Cause Register 1 (Offset 0X61B)
73
Reset Cause Register 2 (Offset 0X61C)
74
BMM Control Register (Offset 0X620)
74
LED Control Register 1 (Offset 0X622)
75
SPI Control Register (Offset 0X625)
75
Pcie SATA SPI Control Register (Offset 0X626)
76
BIT Control/Status Register (Offset 0X629)
76
NOR Flash Page Register (Offset 0X636)
77
AXIS Registers
77
AXIS Timestamp Registers 0 to 5
77
AXIS Clock Frequency Register (Offset 0X64E)
77
AXIS Clock Control Register (Offset 0X64F)
78
Timer Registers
78
Timer 0 Control/Status Register 1 (Offset 0X650), Timer 1 Control/Status Register 1 (Offset 0X658), Timer 2 Control/Status Register 1 (Offset 0X660) and Timer 3 Control/Status Register 1 (Offset 0X668)
78
Timer 0 Control/Status Register 2 (Offset 0X651), Timer 1 Control/Status Register 2 (Offset 0X659), Timer 2 Control/Status Register 2 (Offset 0X661) and Timer 3 Control/Status Register 2 (Offset 0X669)
79
Timer 0 Interrupt Clear Register (Offset 0X652), Timer 1 Interrupt Clear Register (Offset 0X65A), Timer 2 Interrupt Clear Register (Offset 0X662) and Timer 3 Interrupt Clear Register (Offset 0X66A)
79
Timer Data Byte Registers
80
GPIO (7-0) Registers
81
GPIO (7-0) out Register (Offset 0X670)
81
GPIO (7-0) in Register (Offset 0X671)
81
GPIO (7-0) Direction Register (Offset 0X672)
81
GPIO (7-0) Interrupt Enable Register (Offset 0X673)
81
GPIO (7-0) Interrupt Level/Edge Register (Offset 0X674)
81
GPIO (7-0) Interrupt Polarity Register (Offset 0X675)
81
GPIO (7-0) Interrupt both Edges Register (Offset 0X676)
82
GPIO (7-0) Interrupt Status/Clear Register (Offset 0X677)
82
GPIO (7-0) Availability Register (Offset 0X678)
82
GPIO (7-0) Interrupt Select Register (Offset 0X679)
82
GPIO (7-0) Interrupt Non-Maskable Register (Offset 0X67A)
82
GPIO (7-0) Test Mode Register (Offset 0X67B)
83
GPIO (15-8) Registers
83
GPIO (15-8) out Register (Offset 0X67C)
83
GPIO (15-8) in Register (Offset 0X67D)
83
GPIO (15-8) Direction Register (Offset 0X67E)
83
GPIO (15-8) Interrupt Enable Register (Offset 0X67F)
83
GPIO (15-8) Interrupt Level/Edge Register (Offset 0X680)
83
GPIO (15-8) Interrupt Polarity Register (Offset 0X681)
84
GPIO (15-8) Interrupt both Edges Register (Offset 0X682)
84
GPIO (15-8) Interrupt Status/Clear Register (Offset 0X683)
84
GPIO (15-8) Availability Register (Offset 0X684)
84
GPIO (15-8) Interrupt Select Register (Offset 0X685)
84
GPIO (15-8) Interrupt Non-Maskable Register (Offset 0X686)
85
GPIO (15-8) Test Mode Register (Offset 0X687)
85
GPIO (23-16) Registers
85
GPIO (23-16) out Register (Offset 0X688)
85
GPIO (23-16) in Register (Offset 0X689)
85
GPIO (23-16) Direction Register (Offset 0X68A)
85
GPIO (23-16) Interrupt Enable Register (Offset 0X68B)
86
GPIO (23-16) Interrupt Level/Edge Register (Offset 0X68C)
86
GPIO (23-16) Interrupt Polarity Register (Offset 0X68D)
86
GPIO (23-16) Interrupt both Edges Register (Offset 0X68E)
86
GPIO (23-16) Interrupt Status/Clear Register (Offset 0X68F)
86
GPIO (23-16) Availability Register (Offset 0X690)
87
GPIO (23-16) Interrupt Select Register (Offset 0X691)
87
GPIO (23-16) Interrupt Non-Maskable Register (Offset 0X692)
87
GPIO (23-16) Test Mode Register (Offset 0X693)
87
GPIO Availability Debug Register (Offset 0X694)
87
Availability Registers
88
Ethernet Availability Register (Offset 0X6A0)
88
COM Port Availability Register (Offset 0X6A1)
88
COM Port 4-Wire Configuration Register (Offset 0X6A2)
89
COM Port Modem Configuration Register (Offset 0X6A3)
89
SATA Port Availability Register (Offset 0X6A4)
89
USB2.0 Ports 7-0 Availability Register (Offset 0X6A5)
90
USB3.0 Ports 7-0 Availability Register (Offset 0X6A6)
90
USB2.0 Ports 15-8 Availability Register (Offset 0X6A7)
90
USB3.0 Ports 15-8 Availability Register (Offset 0X6A8)
90
Display Availability Register (Offset 0X6A9)
90
VGA Availability Register (Offset 0X6Aa)
91
DVI/HDMI Availability Register (Offset 0X6Ab)
91
Display-Port Availability Register (Offset 0X6Ac)
91
Ancillary/Audio Availability Register (Offset 0X6Ad)
91
Front Panel Configuration Register (Offset 0X6Ae)
92
XMC/PMC Site 1 I/O Configuration Register (Offset 0X6Af)
92
XMC/PMC Site 2 I/O Configuration Register (Offset 0X6B0)
92
SSD Availability Register (Offset 0X6B1)
93
SSD Secure Hardware Erase Capability Register (Offset 0X6B2)
93
COM Port Enable Register (Offset 0X6Bb)
93
COM Port Mode Register (Offset 0X6Bc)
94
COM Port RS485 Auto-Direction Control Enable Register (Offset 0X6Bd)
94
COM Port Loopback Enable Register (Offset 0X6Be)
94
SSD Erase Control Register (Offset 0X6Bf)
95
SSD Cache Flush Control Register (Offset 0X6C0)
95
Scratch Pad Register 1 (Offset 0X6C6)
95
Test Register (Offset 0X6C7)
96
XMC/PMC Site 1 Status Register (Offset 0X6C8)
97
XMC/PMC Site 2 Status Register (Offset 0X6C9)
98
Backplane Status Register (Offset 0X6Ca)
98
SSD Status Register (Offset 0X6Cb)
99
Write Protection Status Register (Offset 0X6Cc)
99
Jumper Link Status Register (Offset 0X6Cd)
100
Boot Location Status Register (Offset 0X6Ce)
101
Thermal Status Register (Offset 0X6D0)
101
Alarm Status Register (Offset 0X6D1)
102
Interrupt Controller Registers
102
Interrupt Status Register (Low) (Offset 0X6E0)
103
Interrupt Status Register (High) (Offset 0X6E1)
103
Interrupt Enable Register (Low) (Offset 0X6E2)
103
Interrupt Enable Register (High) (Offset 0X6E3)
103
Interrupt Select Register (Low) (Offset 0X6E4)
103
Interrupt Select Register (High) (Offset 0X6E5)
103
Interrupt Non-Maskable Register (Low) (Offset 0X6E6)
103
Interrupt Non-Maskable Register (High) (Offset 0X6E7)
103
Availability/Configuration Register (Offset 0X6E8)
104
Reset Control Register (Offset 0X6E9)
104
EEPROM DIP Switch 1 Configuration Register 0 (Offset 0X6Ea)
105
EEPROM DIP Switch 1 Configuration Register 1 (Offset 0X6Eb)
105
Configuration Unlock Password Register (Offset 0X6Ec)
106
Control Register (Offset 0X6Ed)
106
Scratch Pad Register 2 (Offset 0X6Ee)
106
LED Control Register 2 (Offset 0X6Ef)
106
Flash Password Registers (Offsets 0X6F0 to 0X6F7)
107
EEPROM DIP Switch 2 Configuration Register 1 (Offset 0X6Fa)
107
EEPROM DIP Switch 2 Configuration Register 2 (Offset 0X6Fb)
107
Watchdog Registers
107
Watchdog Configuration Register (Offset 0X700)
107
Watchdog Prescaler (Low Byte) Register (Offset 0X701)
108
Watchdog Enable Register (Offset 0X702)
108
Watchdog Status Register (Offset 0X703)
108
Watchdog Kick Register (Offset 0X704)
109
Watchdog Interrupt Acknowledge Register (Offset 0X705)
109
Watchdog Main Counter Low Byte Register (Offset 0X706)
109
Watchdog Main Counter High Byte Register (Offset 0X707)
109
Watchdog Warning Timer Bits 8:1 Register (Offset 0X708)
109
Watchdog Warning Timer Bits 16:9 Register (Offset 0X709)
109
Watchdog Minimum Threshold Low Byte Register (Offset 0X70A)
110
Watchdog Minimum Threshold High Byte Register (Offset 0X70B)
110
Watchdog Warning Threshold Low Byte Register (Offset 0X70C)
110
Watchdog Warning Threshold High Byte Register (Offset 0X70D)
110
Watchdog Maximum Threshold Low Byte Register (Offset 0X70E)
110
Watchdog Maximum Threshold High Byte Register (Offset 0X70F)
110
Scratchpad Memory Registers (Offset 0X720 to 0X72F)
111
BMM UART Registers (Offsets 0X0 to 0X7)
111
6 Connectors
112
Table 6-1 Connector Functions
112
Figure 6-1 Front Connector Positions
112
Figure 6-2 Rear Connector Position
113
Backplane Connectors
114
P0 Connector
114
Table 6-2 P0 Pin Assignments
114
P1 Connector
115
Table 6-3 P1 Pin Assignments
115
P2 Connector
116
Table 6-4 P2 Pin Assignments
116
Backplane Signal Definitions
117
Table 6-5 Backplane Connector Signal Definitions
117
Figure 6-3 RS422/485 Signal Waveforms
118
PMC Connectors
119
J11/J21 and J12/J22 Connectors
119
Table 6-6 J11/J21 Pin Assignments
119
Table 6-7 J12/J22 Pin Assignments
119
J13/J23 Connector
120
Table 6-8 J13/J23 Pin Assignments
120
J14/J24 Connector
121
Table 6-9 J14 Pin Assignments
121
Table 6-10 J24 Pin Assignments
121
PMC Signal Descriptions
122
Table 6-11 PMC Signal Descriptions
122
XMC Connectors
123
J15/J25 Connector
123
Table 6-12 J15/J25 Pin Assignments
123
J16 Connector
124
Table 6-13 J16 Pin Assignments
124
XMC Signal Descriptions
125
Table 6-14 XMC Signal Descriptions
125
Test and Programming Headers
126
P16 (Reserved)
126
P14 (Test Access Card Connector)
126
A • Specifications
127
Technical Specification
127
Table A-1 Technical Data
127
Electrical Specification
128
Table A-2 Voltage Supply Requirements
128
Table A-3 Current Consumption
128
Reliability (MTBF)
129
Mechanical Specification
129
Table A-4 Reliability (MTBF)
129
Table A-5 Mechanical Construction
129
Product Codes
130
Table A-6 Product Options
130
Software Support
131
Boot Firmware
131
Built in Test
131
Background Condition Screening
132
I/O Modules
132
Test Access Card
132
Development Systems
132
B • Statement of Volatility
133
Volatile Memory
133
Non-Volatile Memory
133
Table B-1 Volatile Memory
133
Table B-2 Non-Volatile Memory
133
C • Ppcx Compatibility
135
Ppc4A
135
P0 Connector
135
P1 Connector
136
P2 Connector
137
P2 Connector Alternative
138
Ppc7A
139
P0 Connector
139
P1 Connector
140
P2 Connector
141
P2 Connector Alternative
142
Ppc7D
143
P0 Connector
143
P0 Connector Alternative
144
P1 Connector
145
P2 Connector
146
P2 Connector Alternative
147
Ppc10A
148
P0 Connector
148
P0 Connector Alternative
149
P1 Connector
150
P2 Connector
151
P2 Connector Alternative 1
152
P2 Connector Alternative 2
153
100 C • Ppcx Compatibility (Continued)
148
Glossary
154
Index
155
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