JVC XV-S62SL Service Manual page 33

MN67706ZY (IC201) : Auto digital servo controller
1.Pin layout
CHCK40
DAT3
DAT2
DAT1
DAT0
33VSS
33VDD
TX
XRESET
ENS
ENC
CPUIRQ
CPUCLK
CPUDTIN
CPUDTOUT
MONA
MONB
MONC
NC
25VSS
25VDD
LDCUR(AD6)
TDOFS(AD5)
TG(AD4)
RFENV(AD3)
2.Pin functions (1/3)
Pin No. Symbol
1 AS(AD2)
2 TE(AD1)
3 FE(AD0)
4 AVDD
5 FODRV(DA1)
6 TRDRV(DA0)
7 AVSS
8 ARF
9 NARF
10 IREF1
11 IREF2
12 DSLF1
13 DSLF2
14 AVDD
15 VHALF
16 PLPG
17 PLFG
18 VREFH
19 RVI
20 AVSS
21 PLFLT1
22 PLFLT2
23 JITOUT
24 RFDIF
25 CSLFL1
76
77
78
79
80
81
82
83
84
85
86
87 MN67706ZY
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
I AS : Full adder signal(FEP)
I Phase difference/3 beam tracking error(FEP)
I Focus error(FEP)
- Apply 3.3V(For analog circuit)
O Focus drive(DRVIC)
O Tracking drive(DRVIC)
- Ground(For analog circuit)
I Equivalence RF+(FEP)
I Equivalence RF-(FEP)
I Reference current1(For DBAL)
I Reference current2(For DBAL)
I/O Connect to capacitor1 for DSL
I/O Connect to capacitor2 for DSL
- Apply 3.3V(For analog circuit)
I Reference voltage 1.65+-0.1V(FEP)
- Not use(PLL phase gain setting resistor terminal)
- Not use(PLL frequency gain setting resistor terminal)
I Reference voltage 2.2V+-0.1V(FEP)
I/O Connect to resistor for VREFH reference current source
- Ground(For analog circuit)
O Connect to capacitor1 for PLL
O Connect to capacitor2 for PLL
I/O Output for jitter signal monitor
I Not use
I/O Pull-up to VHALF
TSTSG
50
BDO
49
SYSCLK
48
OFTR
47
33VDD
46
33VSS
45
FBAL
44
TBAL
43
TGBAL
42
AVSS
41
ROUT
40
LOUT
39
AVDD
38
JLINE
37
DBALO
36
VCOF
35
TRCRS
34
CMPIN
33
LPFOUT
32
LPFIN
31
AVSS
30
HPFOUT
29
HPFIN
28
AVDD
27
VFOSHORT
26
Description
XV-S62SL
1-33