JVC XV-S62SL Service Manual page 37

3.Pin function (NDV8601VWA-BB 2/4)
Symbol
Pin No.
30
MA11
31
VSSio
32,33
MA12,13
34
VDD
35
CS0
36
VDDio
37
RAS
38
CAS
39
WE
40
VSSio
41
DQM0
42
DQM2
43
MD16
44
VDDio
45,46
MD17,18
47
VSS
48
MD19
49
VSSio
50~52
MD20~22
53
VDDio
54~56
MD23~25
57
VSSio
58~61
MD26~29
62
VDDio
63,64
MD30,31
65
DQM3
66
CS1
67
VSSD
68
SPDIF
69
VSSio
70
AIN
71
AOUT3
72
AOUT2
73
AOUT1
74
AOUT0
75
VDDio
76
PCMCLK
77
VDD
78
ACLK
79
LRCLK
80
SRST
81
RSTP
82
VSSio
83
RXD1
84
SSPIN1
85
VSS
86
SSPOUT1
87
SSPCLK1
88
SSPCLK0
89
VDD
90
SSPIN0
I/O
Non connect
-
- Connect to ground
SDRAM Address bus, reserved for terminal compatibility with 64Mb SDRAM
O
Power supply terminal 1.8V
-
SDRAM Primary bank chip select
O
Power supply terminal 3.3V
-
O SDRAM Command bit
SDRAM Command bit
O
SDRAM Command bit
O
Connect to ground
-
SDRAM Data byte enable
O
O SDRAM Data byte enable
SDRAM Data bus terminal
I/O
Power supply terminal 3.3V
-
SDRAM Data bus terminal
I/O
Connect to ground
-
I/O SDRAM Data bus terminal
Connect to ground
-
SDRAM Data bus terminal
I/O
Power supply terminal 3.3V
-
SDRAM Data bus terminal
I/O
Connect to ground
-
SDRAM Data bus terminal
I/O
- Power supply terminal 3.3V
SDRAM Data bus terminal
I/O
SDRAM Data byte enable
O
SDRAM Extension bank chip select
O
Connect to ground
-
O S/PDIF Digital audio output terminal
Connect to ground
-
Digital audio input for digital micro; can be used as GPIO
I
Serial audio output data to audio DAC for left and right channels for down-mix
O
Serial audio output data to audio DAC for surround left and right channels
O
O Serial audio output data to audio DAC for center and LFE channels
Serial audio output data to audio DAC for left and right channels
O
Power supply terminal 3.3V
-
Audio DAC PCM sampling clock frequency, common clock for DACs and ADC
O
Power supply terminal 1.8V
-
O Audio interface serial data clock, common clock for DACs and AD converter
Left / right channel clock, common clock for DACs and ADC
O
Active low RESET signal for peripheral reset
O
RESET_Power : from system, used to reset frequency synthesizer and rest
I
of chip
- Connect to ground
UART1 Serial data input from external serial device, used for IR receiver
I
SSP1 Data in or 16X clock for USART function in UART1
I/O
Connect to ground
-
SSP1 Data out or UART1 data-terminal-ready signal
I/O
SSP1 Clock or UART1 clear-to -send signal
I/O
SSP0 Clock or request-to-send function in UART1
I/O
- Power supply terminal 1.8V
SSP0 Data in or 16X clock for USART function in UART0
I/O
Description
XV-S62SL
1-37