JVC XV-S62SL Service Manual page 34

XV-S62SL
2.Pin function (2/3)
Pin No. Symbol
26 VFOSHORT
27 AVDD
28 HPFIN
29 HPFOUT
30 AVSS
31 LPFIN
32 LPFOUT
33 CMPIN
34 TRCRS
35 VCOF
36 DBALO
37 JLINE
38 AVDD
39 LOUT
40 ROUT
41 AVSS
42 TGBAL
43 TBAL
44 FBAL
45 33VSS
46 33VDD
47 OFTR
48 SYSCLK
49 BDO
50 TSTSG
51 TRSDRV
52 SPDRV
53 FG
54 TILTP
55 TILT
56 TILTN
57 25VSS
58 25VDD
59 DTRD
60 IDGT/TEMUTE
61 LRCK/CPDET2
62 BLKCK/CPDET1
63 SBCK/PLLOK
64 IDHOLD
65 DACLRCK/JMPINH
66 DACDATA/LG
67 NTRON
68 DACCLK
69 IPFLAG
70 SUBC
71 NCLDCK/JUMP
72 MINTEST
73 TEST
74 33VSS
75 33VDD
76 CHCK40
77 DAT3
78 DAT2
79 DAT1
80 DAT0
1-34
I/O
O VFO short output
- Apply 3.3V(For analog circuit)
I Pull-up to VHALF
O Connect to TP208
- Ground(For analog circuit)
I Pull-up to VHALF
O Not use
I Connect to TP210
I Input signal for track cross formation
I/O JFVCO control voltage
O DSL balance adjust output
O J-line setting output(FEP)
- Apply 3.3V(For analog circuit)
O Connect to TP203 (Analog audio left output)
O Connect to TP204 (Analog audio right output)
- Ground(For analog circuit)
O Tangential balance adjust(FEP)
O Tracking balance adjust(FEP)
O Focus balance adjust(FEP)
- Ground(For I/O)
- Apply 3.3V(For I/O)
I Off track signal
I 16.9344MHz system clock input(ODC)
I Drop out(FEP)
O Calibration signal(FEP)
O Traverse drive(DRVIC)
O Spindle drive output(DRVIC)
I FG signal input (Spindle motor driver)
O Connect to TP205
O Connect to TP206
O Connect to TP207
- Ground(For internal core)
- Apply 2.5V(For internal core)
I Data read control signal(ODC)
I Pull-down to Ground
O LR channel data strobe(ODC)/
O CD sub code synchronous signal(ODC)/
I CD sub code data shift clock(ODC)/PLL pull-in OK signal input
I Pull-down to Ground
I 1bit DAC-LR channel data strobe(ODC)/
I CD 1bit DAC channel data(ODC)
O L : Tracking ON(ODC)
O 1bit DAC channel data shift clock(ODC)
O CIRC error flag(ODC)
O CD sub code(ODC)
O CD sub code data frame clock(ODC)/DVD JUMP signal(ODC)
I Pull-down to Ground(For MINTEST)
I Pull-down to Ground(For TEST)
- Ground(For I/O)
- Apply 3.3V(For I/O)
O Clock for SRDATA(ODC)
O SRDATA3(ODC)
O SRDATA2(ODC)
O SRDATA1(ODC)
O SRDATA0(ODC)
Description