JVC XV-521BK Service Manual page 37

Symbol
I/O
Pin No.
149 VDD-3.3 -
150 VDATA4 O
151 VSS -
152 VDATA5 O
153 PIO7 I/O
154 VDATA6 O
155 VDATA7
156 PIO8 I/O
157 HSYNC I/O
158 VSYNC I/O
159 DA-IEC O
160 VDD-3.3 -
161 DA-DATA0 O
162 VSS -
163 DA-DATA1
164 DA-DATA2 O
165 DA-DATA3
166 DA-LRCK O
167 DA-BCK O
168 VDD-2.5 -
169 DA-XCK I/O
170 VSS -
171 DAI-DATA I
172 DAI-LRCK I
173 DAI-BCK I
174 PIO9 I/O
175 CLKSEL I
176 A-VDD -
177 VCLK I
178 SYSCLK I
179 A-VSS -
180 I
DVD-DATA0
/CD-DATA
181 -
VDD-3.3
182 I
DVD-DATA1
/CD-LRCK
183 VSS -
184 I
DVD-DATA2
/CD-BCK
185 I
DVD-DATA3
/CD-C2PO
Function
3.3-V supply voltage for I/O signals.
Video data buses for byte sequential CbYCrY data.
The decoder does not run VDATA during the power up procedure. However,
during booting the decoder uses operational configuration parameters or 3-state VDATA.
Ground for core logic and I/O signals.
Video data buses for byte sequential CbYCrY data.
The decoder does not run VDATA during the power up procedure. However,
during booting the decoder uses operational configuration parameters or 3-state VDATA.
Programmable I/O pin. Input mode after resetting.
Video data buses for byte sequential CbYCrY data.
The decoder does not run VDATA during the power up procedure. However,
during booting the decoder uses operational configuration parameters or 3-state VDATA.
Programmable I/O.
pins. Input mode after reset.
Horizontal sync. The decoder begins outputting pixel data for a new horizontal line
after the falling (active) edge of HSYNC.
Vertical sync.Bi-directional, the decoder outputs the top border of a new field on the
first HSYNC aftre the falling edge of VSYNC. VSYNC can accept vertical
synchronization or top/bottom field notification from an external source.
(VSYNC HIGH = bottom field. VSYNC LOW = Top field)
Bistream data in IEC-1937 or PCM data out in IEC-958 format.
3.3-V supply voltage for I/O signals.
PCM data out, eight channels. Serial audio samples relative to DA-BCK clock.
Ground for core logic and I/O signals.
PCM data out, eight channels. Serial audio samples relative to DA-BCK clock.
PCM left-right clock. Identifies the channel for each audio sample. the polarity is
programmable.
PCM bit clock. Divided by 8 from DA-XCK can be either 48 or 32 times the sampling
clock.
2.5-V supply voltage for core logic.
Audio master frequency clock. Used to generate DA-BCK and DA-LRCK. DA-XCK can
be eigher 384 or 256 times the sampling frequency.
Ground for core logic and I/O signals.
PCM input data. two channels. Serial audio samples relative to DAI-BCK clock.
PCM input left-right clock.
PCM input bit clock.
Programmable I/O pins. Input mode after reset.
Clock Select: Internal = VDD, External = VSS
3.3-V analog supply voltage.
Video clock. Clocks out data on input. VDATA7.Clock is typically 27 MHz.
System clock.Decoder requires external 27 MHz TTL oscilator.
Drive with the same 27-MHz as VCK.
Analog ground for PLL
Serial CD data. This pin is shared with DVD compressed data DVD-DATA0.
3.3-V supply voltage for I/O signals.
Programmable polarity 16-bit word synchronization to the decoder
(right channel HIGH). This pin is shared with DVD compressed data DVD-DATA1.
Ground for core logic and I/O signals.
CD bit clock. Decoder accept multiple BCK rates. This pin is shared with DVD
compressed data DVD-DATA2.
Asserted HIGH indicates a corrupted byte.Decoder keeps the previous valid picture
on-screen unit the next valid picture is decoded. This pin is shares with DVD
compressed data DVD-DATA3.
XV-521BK/523GD/525BK/421BK
ZIVA3-PEO (4/5)
1-37