JVC XV-521BK Service Manual page 36

XV-521BK/523GD/525BK/421BK
Symbol
I/O
Pin No.
99 MADDR8 O
100 MADDR10
101 VDD-3.3 -
102 MADDR7 O
103 VSS -
104 MADDR0
105 MADDR6 O
106 MADDR1
107 VDD-3.3 -
108 MADDR5 O
109 VSS -
110 MADDR2
111 MADDR4 O
112 MADDR3
113 VDD-3.3 -
114 NC O
115 VSS -
116 NC O
117 VDD-2.5 -
118 NC O
119 VSS -
120
121 NC O
122
123 VDD-3.3 -
124 NC O
125 VSS -
126 NC O
127
128 O
RESERVED
129 PIO2 I/O
130 NC O
131 I
RESERVED
132
133 PIO3 I/O
134 VDD-3.3 -
135 I
RESERVED
136 VSS -
137 I
RESERVED
138 PIO4 I/O
139 I
RESERVED
140
141 PIO5 I/O
142 VDATA0 O
143 VDATA1
144 VDD-2.5 -
145 VDATA2 O
146 VSS -
147 PIO6 I/O
148 VDATA3 O
1-36
Function
Memory address.
3.3-V supply voltage for I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
3.3-V supply voltage for I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
3.3-V supply voltage for I/O signals.
No Connection
Ground for core logic and I/O signals.
No Connection
2.5-V supply voltage for core logic.
No Connection
Ground for core logic and I/O signals.
No Connection
3.3-V supply voltage for I/O signals.
No Connection
Ground for core logic and I/O signals.
No Connection
Open drain signal, must be pulled-up via 4.7kW to 3.3 volts.
Programmable I/O pins. Input mode after reset.
No Connection
Tie to VSS or VDD-3.3
Programmable I/O pins. Input mode after reset.
3.3-V supply voltage for I/O signals.
Tie to VSS or VDD-3.3
Ground for core logic and I/O signals.
Tie to VSS or VDD-3.3
Programmable I/O pins. Input mode after reset.
Tie to VSS or VDD-3.3
Programmable I/O pins.Input mode after reset.
Video data bus. Byte serial CbYCrY data synchronous with VCLK. At power-up,
the decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA
2.5-V supply voltage for core logic.
Video data bus. Byte serial CbYCrY data synchronous with VCLK. At power-up,
the decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA
Ground for core logic and I/O signals.
Programmable I/O pins. Input mode after reset.
Video data bus. Byte serial CbYCrY data synchronous with VCLK. At power-up,
the decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA
ZIVA3-PEO (3/5)