Advertisement
IC DESCRIPTION-1/2 (MN662782RPT1)-2/2
Pin No.
Pin Name
51
AVDD1
52
FSEL
53, 54
TMOD1, 2
55
FLAG
56
CLVS/IPFLAG
57
EXT0/ISRDATA
58
EXT1/ILRCK
59
EXT2/IBCLK
60
TX
61
MCLK
62
MDATA
63
MLD
64
BLKCK
65
SQCK/BCLK
66
SUBQ/LRCK
67
DMUTE/SRDATA
68
STAT
69
NRST
70
SPPOL
71
PMCK
72
SMCK
73
SUBC/SSYNC
74
SBCK/64FS
75
NCLDCK
76
NTEST
77
X1
78
X2
79
DVDD1
80
DVSS1
I/O
I
Power supply for analog circuit (for audio output block).
I
Noise filter ON/OFF switching input. L: ON. H: OFF.
I
Terminal mode select input terminal 1, 2. Normal: L.
O
Flag signal output. (Not connected)
Command selection .
O
I/O
Command selection.
I/O
Command selection.
I/O
Command selection.
O
Digital audio interface output signal.
I
Microprocessor command clock signal input. (Latches data at raising edge.)
I
Microprocessor command data signal input.
I
Microprocessor command load signal input. L: Load.
Sub-code block clock signal. fBLKCK=75 Hz (during normal playback)/SYNC signal
O
for CDTEXT (DQSY) fDQSY=300 Hz (during normal playback).
I/O
Command selection.
O
Command selection.
I/O
Command selection.
Status signal. (CRC, RESY, CLVS, NTTSTOP, SQOK, FLAG6, SENSE, NFLOCK,
O
NTLOCK, BSSEL, SUBQ data, CDTEXT data, anti-shock read-out data)
I
Reset input. L: Reset.
O
Spindle motor drive signal output (polarity output).
O
88.2 KHz clock signal output.
O
4.2336 MHz clock signal output.
O
Command selection.
I
Command selection.
O
Sub-code frame clock signal output. (fCLDCK=7.35 KHz) (Not connected)
I
Test terminal: Normally H.
I
Crystal oscillator circuit input terminal. f=16.9344 MHz.
O
Crystal oscillator circuit output terminal. f=16.9344 MHz.
I
Power supply for digital circuit.
I
Ground for digital circuit.
Description
• Spindle servo phase sync signal output. H: CLV. L: Rough servo.
• Interpolation flag signal output.H: Interpolation. (Not connected)
• Extended input/output port 0.
• SRDATA input. (Not connected)
• Extended input/output port 1.
• LRCK input. H: Lch audio data. L: Rch audio data. (Not connected)
• Extended input/output port 2.
• BCLK input. (Not connected)
• External clock input for sub-code Q register.
• Bit clock output for SRDATA.
• Sub-code Q data output.
• L, R identification signal output. H: Lch audio data. L: Rch audio data.
• Muting input. H: Mute.
• Serial data output.
• Sub-code serial output.
• Sector SYNC output. (Not connected)
• Clock input for sub-code serial output.
• 64 FS output. (Not connected)
-19-
Advertisement
