Aiwa CSD-A170 Service Manual page 18

IC, LC78622ED
Pin No. Pin Name I/O
1 DEFI I Defect sense signal (DEF) input pin. (Connect to 0V when not used).
2 TAI I
3 PDO O
4 VVSS —
For PLL.
5 ISET I
6 VVDD —
7 FR I
8 VSS — Digital system GND. Be sure to connect to 0V.
9 EFMO O
For slice level control.
10 EFMIN I
11 T2 I Test signal input pin with built-in pull-down resistor. Be sure to connect to 0V.
12, 13 CLV+, CLK- O Disc motor control output. Three level output is possible using command.
Rough servo or phase control automatic selection monitoring output pin. Rough servo
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14 V/P O
at H. Phase servo at L.
15 HFL I Track detect signal input pin. Schmidt input.
16 TES I Tracking error signal input pin. Schmidt input.
17 TOFF O Tracking OFF output pin.
18 TGL O Tracking gain selection output pin. Gain boost at L.
19, 20 JP+, JP- O Track jump control signal output pin. Three level output is possible using command.
21 PCK O EFM data playback clock monitoring pin 4.3218 MHz when phase is locked in.
Sync signal detection output pin. H when the sync signal which is detected from EFM
22 FSEQ O
signal and thesync signal which is internally generated agree.
23 VDD — Digital system power supply pin.
24 SL+ O Moves the sled to outer circumference.
25 SL- O Moves the sled to inner circumference.
26 — — Not connected.
27 PUIN I CD pickup inner switch detection.
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28 RW O Read, wright signal.
29 EMPH O De-emphasis monitor output pin. De-emphasis disc is being played back at H.
30 C2F O C2 flag output pin.
31 DOUT O DIGITAL OUT output pin. (EIAJ format).
32, 33 T3, T4 I Test signal input pin with built-in pull-down resistor. Be sure to connect to 0V.
34 N.C. — Not used. Set the pin to open.
35 MUTEL O
36 LVDD —
L-channel 1-bit DAC.
37 LCHO O
38 LVSS —
39 RVSS —
40 RCHO O
R-channel 1-bit DAC.
41 RVDD —
42 MUTER O
Description
Test signal input pin with built-in pull-down resistor. Be sure to connect to 0V.
Phase comparator output pin to control external VCO.
GND pin for built-in VCO. Be sure to connect to 0V.
Pin to which external resistor adjusting the PD0 output current.
Power supply pin for built-in VCO.
Pin for VCO frequency range adjustment.
EFM signal output pin.
EFM signal input pin.
L-channel mute output pin.
L-channel power supply pin.
L-channel output pin.
L-channel GND. Be sure to connect to 0V.
R-channel GND. Be sure to connect to 0V.
R-channel output pin.
R-channel power supply pin.
R-channel mute output pin.
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Pin No. Pin Name I/O
43 XVDD — Crystal oscillator power supply pin.
44 XOUT O
Pin to which external 16.9344 MHz crystal oscillator is connected.
45 XIN I
46 XVSS — Crystal oscillator GND pin. Be sure to connect to 0V.
47 SBSY O Subcode block sync signal output pin.
48 EFLG O C1, C2, single and dual correction monitoring pin.
49 PW O Subcode P, Q, R, S, T, U and W output pin.
50 SFSY O Subcode frame sync signal output pin. Falls down when subcode enters standby.
Subcode read clock input pin. Schmidt input. (Be sure to connected to 0V when not
51 SBCK I
in use.)
Pin outputting the 7.35 kHz sync signal which is generated by dividing frequency of
52 FSX O
crystal oscillator.
53 WRQ O Subcode Q output standby output pin.
54 RWC I Read/write control input pin. Schmidt input.
55 SQOUT O Subcode Q output pin.
56 COIN I Command input pin from microprocessor.
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57 CQCK I Command input read clock or subcode read input clock from SQOUT pin
58 RES I LC78622 reset input pin. Set this pin to L once when the main power is turned on.
59 T11 O Test signal output pin. Use this pin as open (normally L output).
60 16M O 16.9344 MHz output pin.
61 4.2M O 4.2336 MHz output pin.
62 T5 I Test signal input pin with built-in pull-down resistor. Be sure to connect to 0V.
Chip select signal input pin with built-in pull-down resistor. Be sure to connect to 0V
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63 CS I
while it is not controlling.
64 T1 I Test signal input pin without built-in pull-down resistor. Be sure to connect to 0V.
Description
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