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SIGNAL NAME
RESET-
BUSRQ-
(Bus Request)
BUSAK-
(Bus
Acknowledge)
ClK
(Clock)
Table 3-4. Z-80B CPU Signals (Continued)
FUNCTION
Input, active low.
Forces the Z-80B CPU program counter to zero
and initializes the Z-80B CPU.
Input, active low.
110 devices and memory use this signal to
request control of the CPU address bus, data
bus, and tri-state control signals.
Output, active low.
Asserted by the CPU to grant the requesting
device control of the CPU address bus, data
bus, and tri-state control signals.
Single-phase CMOS level CPU clock input.
Maximum
input frequency is 4 MHz.
This clock is driven at
3.6864 MHz (PHI signal) in the MUX card,
3-11
HP 27130A
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