Regi5Ter 8 - Dma A Configuration; Register 9 Lower Byte Of Transfer Byte Count; Register Adma A I/O Port Address; Register B Interrupt Vector - HP 27130A Technical Reference Manual

HP 27130A
Register 8 - DMA A Configuration. The functions of the bits of register 8 (read/write) are as
follows:
Bit 7
=
DMA channel A enable bit
1
=
enable
0= disable
Bit 6
=
Transfer to/from memory
1 = to memory
0=
from memory
Bit 5
=
Direction of memory address counter
1
=
decrement counter
0= increment counter
. Bit
4 =
DMA channel A interrupt enable
Bit 3
1
=
enable interrupt
o
=
disable interrupt
Bit 2 Upper four bits of transfer byte count for DMA A
Bit 1
Bit 0
NOTE
Bits 4 through 7 are zeroed on reset. Bits 0 through
3 are not affected by reset.
Register 9 - Lower Byte of Transfer Byte Count - Channel A. Register 9 (read/write) contains the
lower byte of the transfer byte count for channel A. This register is not affected by reset.
Register A - DMA A I/O Port Address. Register A (read/write) contains the DMA A I/O port
address. This register is not affected by reset.
Register B -Interrupt Vector. Register
a
(read/write) contains interrupt vector information.
Bits 3 through 7 of register B contain bits 3 through 7 of the interrupt vector address. Bits 1
and 2 of the register are modified automatically. by the highest priority device requesting interrupt
service. Table 3-9 shows how bits 1 and 2 are determined based on the interrupts sensed at inter-
rupt acknowledge time. Bit 0 is always a logical zero. Note that this register is not affected by reset.
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