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PRINCIPLES OF OPERA TION
1-
~------------------~~
FUNCTIONAL DESCRIPTION
A functional block diagram of the
HP 27130 Eight-Channel Multiplexer is shown in figure
3-1. Reference will also be made to the schematic logic diagram contained in Section VII, figure 7-1.
Note that figure 7-1 consists of five sheets. References to this figure will be as follows: All, 7-1;
C23, 7-1; D37, 7-1, etc., where the first digit
(1,
2, 3, 4, or 5) refers to the sheet number; the com-
bination of letters A through E and numbers 11 through 58 (All, D37, etc.) refer to the quadrants
on the individual sheets; and 7-1 refers to the figure number. For example,
r
quadrant
A11
L
sheet 1
r
quadrant
D37
L
sheet 3
Circuitry contained on the MUX card includes a Backplane Interface Circuit (BIC) gate array and
its support circuits, a Z-SOB microprocessor (CPU), three Z-80 Counter Timer Circuits (CTCs),
four Z- 80 Serial I/O circuits (SI0/2s), up to 16K bytes of EPROM in two 28-pin sockets, a Memory
Interface
Circuit
(MIC)
gate
array,
64K
bytes
of
dynamic
RAM
(48K
available)
RS-422-A/RS-423-A transmitters and receivers (compatible with RS-232-C and CCITT V.2S), and
I/O channel (backplane) and peripheral device panel (frontplane) connectors.
The heart of the MUX card is the Z-SOB CPU (U33, see D24, 7-1), which through a program stored
in EPROM controls the functions of the card.
The Backplane Interface Circuit (BIC, U41, see A14, 7-1) is a custom
gate
array
integrated
circuit which controls the communication and handshaking with the I/O channel (backplane).
The BIC is accessed by the Z-SOB CPU as an I/O device for control information, and through Direct
Memory Access (DMA) for data transfer to memory.
The Counter Timer Circuits (CTC, U51, U61, and
U71, see E43, 7-1) divide the system clock to
provide baud rate clocks and other necessary clocks for the MUX. They are accessed by the Z-80B
CPU as I/O devices.
The Memory Interface Circuit (MIC, U54, see A32, 7-1) is a custom gate array integrated circuit
which handles dynamic refresh and address multiplexing for the 64K bytes of dynamic RAM. The
MIC also contains the PMA controller, provides interrupt vectors for backplane interrupts,
decodes addresses and provides wait states for the slow EPROMs, and provides reset for the for the
rest of the MUX card.
The Serial
1/
0 circuits (SIOs, U 4 3, U 5 3, U 63 and U 73, see A 4 2, 7 -1) and their associ a ted m ul ti -
plexers, receivers, and drivers (see figure 7 -1, sheet 5), provide serial data communication to the
frontplane connector J2.
3-1
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