Model 64100A - Performance Verification
Operation:
a. The SYSTEM BUS TEST takes the PHI chip off line and reads and writes to
various registers in the PHI chip.
b. The transceiver lines and the cable to the rear panel HPIB connector are
not presently being checked.
c. If a failure occurs, see section IV of the I/O tab.
d. This test may take up to two minutes if a failure occurs.
4-24.
RS232 TEST PROCEDURE.
Purpose:
This test checks proper operation of the USART
(U28 I/O PCB)
and the data
and control circuitry associated with RS-232.
Area Tested:
The 8251 USART, the baud rate generator, loop-back relays, line drivers, the
interface to the CPU, and the rear panel cable.
Operation:
a. Energizes the loop back relays to loop transmit data, and handshake lines
back on receive data.
b. Sends a character stream.
c. compares receive character stream to the transmit character stream.
d. Notes:
1. The voltage
translators
cannot be signaturized
on the higher voltage side.
2. This
test may
take up to
two minutes for a
failure to
be
detected. See section IV of the I/O
tab for more information.
4-25.
PV ON THE EXISTING LOCAL MASS STORAGE OPTION.
MF 4-20
NOTE
If the mainframe under test
contains a
floppy
disc
op~ion
then PV for the floppy disc will
be
given and
explained
in
the
floppy service
manual. If the mainframe contains the
cassette
tape option then
the
PV will be explained in
the tape controller service manual.