Ram Subsystem; Direct Memory Access (Dma) - IBM 5170 Technical Reference

RAM Subsystem
The system board's RAM subsystem starts at address hex 000000
of the 16M address space. It consists of either 256Kb or 512Kb
of 128K by 1-bit RAM modules. Memory access time is 150
nanoseconds and the cycle time is 275 nanoseconds.
Memory-refresh requests one memory cycle every 15
microseconds through the timer/counter (channell). The RAM
initialization program performs the following functions:
• Initializes channel 1 of the timer/counter to the rate
generation mode, with a period of 15 microseconds.
• Performs a memory write operation to any memory location
Note: The memory must be accessed or refreshed eight times
before it can be used.
Direct Memory Access (DMA)
The system supports seven DMA channels. Two Intel 8237 A-5
DMA Controller Chips are used, with four channels for each
chip. The DMA channels are assigned as follows:
Ctlr1
Ctlr2
Ch 0 - Spare
Ch 4 - Cascade for Ctlr 1
Ch 1 - SDLC Ch 5 - Spare
Ch 2 - Diskette (IBM Ch 6 - Spare
Personal Computer)
Ch 3 - Spare Ch 7 - Spare
DMA Channels
DMA controller 1 contains channels 0 through 3. These channels
f"..
support 8-bit data transfers between 8-bit I/O adapters and 8- or
1-12 System Board