Programming The 16-Bit Dma Channels - IBM 5170 Technical Reference

Addresses for all DMA channels do not increase or decrease
through page boundaries (64Kb for channels 0 through 3 and
128Kb for channels 5 through 7).
Programming the 16-Bit DMA Channels
DMA channels 5 through 7 perform 16-bit data transfers. Access
can be gained only to 16 bit devices (I/O or memory) during the
DMA cycles of channels 5 through 7. Access to the DMA
controller (8237 A-5), which controls these channels, is through
I/O addresses
oeo
through ODF. The command codes for the
DMA controller are as follows:
Hex Command Codes
Address
OCO CHO base and current address
OC2 CHO base and current word count
OC4 CH 1 base and current address
OC6 CH1 base and current word count
OC8 CH2 base and current address
OCA CH2 base and current word count
OCC CH3 base and current address
aCE CH3 base and current word count
000 Read Status Register/Write Command Register
002 Write Request Register
004
Write Single Mask Register Bit
006 Write Mode Register
008 Clear Byte Pointer Flip- Flop
aDA
Read Temporary Register/Write Master Clear
ODC Clear Mask Register
ODE Write All Mask Register Bits
DMA Controller Registers
All DMA memory transfers made with channels 5 through 7 must
occur on even-byte boundaries. When the base address for these
channels is programmed, the real address divided by 2 is the data
that is written to the base address register. Also, when the base
word count for channels 5 through 7 is programmed, the count is
the number of 16-bit words to be transferred. Therefore, DMA
channels 5 through 7 can transfer 65,536 words or 128Kb
~
maximum for any selected page of memory. These DMA
channels divide the 16Mb memory space into 128Kb pages.
When the DMA page registers for channels 5 through 7 are
1-14 System Board