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IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
IC10 : ES6629 VIDEO PROCESSOR-(5)
Table 1
ES6629 Pin Description (Continued)
Names
Pin Numbers
TWS
SEL_PLL2
116
TSD0
117
SEL_PLL0
TSD1
118
SEL_PLL1
TSD[2:3]
120, 121
MCLK
122
TBCK
123
SPD_DOBM
SEL_PLL3
124
SPDIF_IN
125
WBLCLK
128
WBL
129
LG
130
IP2
131
IP1
132
FLAG[3:0]
133:136
TEXI
139
TESTAD
140
SBAD
141
FEI
142
I/O
Definitions
O
Audio transmit frame sync output.
I
System and DSCK output clock frequency selection is made at the rising edge of
RESET#. The matrix below lists the available clock frequencies and their
respective PLL bit settings. Strapped to VCC or ground via 4.7-k resistor; read-
only during reset.
SEL_PLL2
SEL_PLL1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
O
Audio transmit serial data port 0.
I
Refer to the description and matrix for SEL_PLL2 pin 116.
O
Audio transmit serial data port 1.
I
Refer to the description and matrix for SEL_PLL2 pin 116.
O
Audio transmit serial data ports 2 and 3.
I/O
Audio master clock for audio DAC.
O
Audio transmit bit clock.
O
S/PDIF output.
I
Clock source select. Strapped to VCC or ground via 4.7-k
during reset.
SEL_PLL3
Clock Source
0
Crystal oscillator
1
CLK input
I
S/PDIF input; (5V tolerant input).
O
DVD-RAM wobble detector circuit clock source to preamp.
O
DVD-RAM wobble output.
O
DVD-RAM land/groove flag.
I
DVD-RAM header position index 2.
I
DVD-RAM header position index 1.
O
To monitor servo status.
I
High-speed tracking error input.
I
Test AD input.
I
Sub-beam addition input signal.
I
Focus input error signal.
SEL_PLL0
Clock Type (MHz)
0
CLK
.5
1
CLK
5.0
0
Bypass
1
CLK
4.0
0
CLK
4.25
1
CLK
4.75
0
CLK
5.5
1
CLK
6.0
resistor; read only
DV-SP302
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