Antenna Switch; Receiver Front End - Motorola HT 1000 series Theory/Troubleshooting Manual

the SRL. The loop divider adds or subtracts phase to
the prescaler divider by changing the divide ratio via the
modulus control line. The output of the prescaler is then
applied to the loop divider. The output of the loop divider
is then applied to the phase detector. The phase detec-
tor will then compare the loop divider's output signal with
the signal from U203 (that is divided down after it is
applied to pin 14 of U204). The result of the signal com-
parison is a pulsed dc signal which is applied to the
charge pump. The charge pump outputs a current that
will be present at pin 32 of U204. The loop filter (which
consists of capacitors C237, C238, C246, C275, C239,
and C240, and resistors R212, R211, R213, and R241)
will transform this current into a voltage that will be
applied to pins 1 and 7 of U205, and alter the VCO's
output frequency.
In order to modulate the PLL, the two-spot modula-
tion method is utilized. The analog modulating signal is
applied to the A/D converter as well as the balance
attenuator, via U204 pin 5. The A/D converter converts
the low frequency analog modulating signal into a digital
code that is applied to the loop divider, thereby causing
the carrier to deviate. The balance attenuator is used to
adjust the VCO's deviation sensitivity to high frequency
modulating signals.
B. Antenna Switch
Switching between the standard and external
antenna ports is accomplished with switch S101 which
is actuated by a plunger located on the accessory
connector.
An electronic PIN diode switch steers RF between
the receiver and transmitter. The common node of the
switch is at capacitor C151. In the transmit mode, RF is
routed to the anode of diode CR108. In receive mode,
RF is routed to pin 1 of U4. In transmit, bias current
sourced from U101 pin 21, is routed through PIN diodes
CR108 and CR109, biasing them to a low impedance
state. Bias current returns to ground through U101 pin
20. In receive, U101 pin 21 is pulled down to ground
and pin 20 is pulled up to B+, reverse biasing diodes
CR108 and CR109 to a high impedance.
C. Receiver Front End
For the purposes of this discussion, the receiver
front end is defined to be the circuitry from the antenna
switch to the output of the IF crystal filter. The 800 MHz
and 900MHz front end is designed to convert the
received RF signal to the 1st IF frequency of 73.35MHz,
while at the same time providing for spurious immunity
and adjacent channel selectivity. A review of the inter-
stage components of the front end will now be
presented with emphasis on troubleshooting considera-
tions.
The received RF signal is passed through the
antenna switch input matching components C151, L127,
tank components C149 & L126 (which are anti-resonant
16
at the radios transmitter frequencies), and output match-
ing components C141 and L30. Both pin diodes CR109
and CR108 must be back biased to properly route the
received signal.
The stage following the antenna switch is a 50-ohm,
inter-digitated, 3-pole, stripline preselector (U4). The
preselector is positioned after the antenna switch to pro-
vide the receiver preamp some protection to strong
signal, out-of-band signals.
After the preselector (U4), the received signal is
processed through the receiver preamp, U1. The
preamp is a dual-gate GaAs MESFET transistor which
has been internally biased for optimum IM, NF, and gain
performance. Components L32 and L34 match the input
(gate 1) of the amp to the first preselector, while at the
same time connecting gate 1 to ground potential. The
output (drain) of the amp is pin 3 and is matched to the
subsequent receiver stage via components L10, C4 and
C88. A supply voltage of 5Vdc is provided to pin 3 via
an RF choke L8 and bypass C31. The 5 volt supply is
also present at pin 4 which connects to a voltage divider
network that biases gate 2 (pin 5) to a predefined quies-
cent voltage of 1.2Vdc. R27 and C11 are connected to
pin 5 to provide amp stability. The FET source (pin 7) is
internally biased at 0.55 to 0.7Vdc for proper operation
with bypass capacitors C13 and C72 connected to the
same node.
The output of the amp is matched to a second 3-
pole preselector (U5) of the type previously discussed.
The subsequent stage in the receiver chain is the 1st
mixer U2, which uses low-side injection to convert the
RF carrier to an intermediate frequency (IF) of
73.35MHz. Since low-side injection is used, the LO fre-
quency is offset below the RF carrier by 73.35MHz, or
Flo = Frf - 73.35MHz. The mixer utilizes GaAs FETs in a
double balanced Gilbert Cell configuration. The LO port
(pin 8) incorporates an internal buffer and a phase shift
network to eliminate the need for a LO transformer. The
LO buffer bypass capacitors C82, C90 and C91 are con-
nected to pin 10 of U2, and should exhibit a nominal dc
voltage of 1.2 to 1.4Vdc. Pin 11 of U2 is LO buffer Vdd
(5Vdc) with associated bypass capacitors C19 and C92
connected to the same node. An internal voltage divider
network within the LO buffer is bypassed to virtual
ground at pin 12 of U2 via bypass C84. The mixer's LO
port is matched to the radio's PLL by a capacitive tap,
C204 and C206. A balun transformer (T1) is used to
couple RF signal into the mixer. The primary of T1 is
matched to the preceding stage by capacitor C7, with
C98 providing a dc block to ground. The secondary of
T1 provides a differential output, with a 180° phase dif-
ferential being achieved by setting the secondary center
tap to virtual ground using bypass capacitors C89, C83
and C86. The secondary of transformer T1 is connected
to pins 1 and 15 of the mixer IC, which drives the source
leg of dual FETs used to toggle the paralleled differential
amplifier configuration within the Gilbert Cell.