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Note: This is a general block diagram. Please see Chapter 5 for details.
J1
Right Slot
PCIE 3.0x16
#1
#1
#2
#2
F
E
#1
#1
#2
#2
D
C
P0PE3
Lane Reversal & Polarity Inversion
x16
J3
Left Slot
x16
PCIE 3.0x16+x16
UL1
I350AM2
JLAN2
JLAN1
RJ45
Figure 1-1. C602 Chipset:
System Block Diagram
x16
PE3
PE2 PE1
CPU Rear
Socket 01
PROCESSOR
P0
P1
QPI
QPI
P0
P1
CPU Front
Socket 00
PROCESSOR
PE3
PE2
PE1
x4 (Lane4~7)
RJ45
1-5
DMI
#1
#1
#2
#2
H
G
#1
#1
#2
#2
B
A
BIOS
DMI
SPI Flash
DMI: Lane Reversal
SPI
DMI
SATA [0...5]
PEG [0...3]
SSB
PCH C602
Gen 3 [1...7]
USB [0...9]
PET8 USB [10,11] LPC
x1
Renesas
VGA
BMC
VGA
PHY
CONN
RTL8211E
IPMI LAN
RJ45
Chapter 1: Introduction
REAR REAR
HW Monitor
Super I/O
W83527 NCT7904D
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