Signal Process Block Diagram - Sony DVP-S7700 Service Manual

3-3. SIGNAL PROCESS BLOCK DIAGRAM

MB-84 BOARD (2/6)
(SEE PAGE 4-19, 4-41)
IC806 0
1.5 Vp-p
DVD RF 10 RF IN1
CD RF 12 RF IN2
RF/SERVO
(SEE PAGE 3-3, 4)
MDS0 43 MDS0
MDP0 48 MDP0
MUTE 110 MUTE
MD2 112 MD2
DFCT 50 DFCT
NORF 51 NORF
LOCK 53 LOCK
FWON 55 FWON
ARPINT 80 XINT
ARPCS 81 XCS
83
ARPWT XWAT
56 57
SYSTEM CONTROL
XWR
(SEE PAGE 3-9, 10)
XRD
DCRCS
DCRINT
DCRWT
AVDRQ
AVCS
AVINT
AVWT
XRST
MRST
IA0-8
ID0-7
05
IC810
16M DRAM
SYSTEM CONTROL
(SEE PAGE 3-9, 10)
96
ı
99
SD0-7
101
ı
106
SDCK, XSHD,
106 XSRO, XSAK, SDEF
ı
109
IC806
ARP
IC806 `⁄¤¤ IC806 `⁄¤›
CD_LRCK, CD_BCK,
106 CD_DATA, SPDIF
ı
109
3.4 Vp-p 27 MHz 3.0 Vp-p 33 MHz
84 122 124 70-73 75-78 56-62 64-67
3-5
IC207
OSD
SO 24 SCLK
25 SIN
SCLKO R OUT 20
CGCSO 26 CS
G OUT 19
B OUT 18
I OUT 17
11 EVEN
12 H SYVC
13 V SYNC
OH SYNC
88
91
1
62
3
64
IC811
SD0-7 DCRSD0-7
ı
74 12
66
77 DTI0-7 DTO0-7
DECRYPT 19
ı 68
79 ı
74
80
AREQ, ALALID,
56
4
ERROR, TOS
59
ı
ı
8
61
43-47 54 26-31 34-41 51
101
102
IC811 %¡
3.4 Vp-p 27 MHz
IC201 IC202
16M SDRAM 16M SDRAM
SDQM, WE, CAS, RAS, CS1, CS2, SDQM, SDCLK
69 VS
70 HS
ı EX_OSD_0-3
IC203
ı
CH-DATA0-7
AV DECODER
21
24
26
30
28 DCK
SPDIF_OUT
98
99
ASDATA
58 59 63-65 68 57 94-96 100 34-39 43-45 47-54
3-6
DVP-S7700
73 FID
74
V SYNC VIDEO
76
(SEE PAGE 3-7)
ı
PD0-7
YC0-7
78
82
ı
84
111 SPDIF
BCLK 105 AV_BCK
AUDIO
(SEE PAGE 3-11)
LRCLK 106 AV_LRCK
107
AV_DATA
384FS
27M_DNR
SYSTEM CONTROL
27M_DSP (SEE PAGE 3-10)
33M