Clarion DXZ955MC Service Manual page 6

EXPLANATION OF IC
Main section
051-2056-00 TB2913HQ
H = Power ON
051-3351-90 BA033CC0FP-E2 Positive Voltage Regurator (3.3V)
GROUND
051-6080-00 LZ9FD51A
Terminal Description
pin 1: D CLK : IN : The data clock pulse input.
pin 2: TEST : O : For the test.
pin 3: RED 0 : O : The red signal input.
pin 4: RED 1 : O : The red signal input.
pin 5: RED 2 : O : The red signal input.
pin 6: RED 3 : O : The red signal input.
pin 7: RED 4 : O : The red signal input.
pin 8: RED 5 : O : Parallel Red data output.
pin 9: GND : - : Ground.
pin 10: VDD : - : Positive voltage supply.
pin 11: GREEN 0 : IN : The green signal input.
pin 12: GREEN 1 : IN : The green signal input.
pin 13: GREEN 2 : IN : The green signal input.
pin 14: GREEN 3 : IN : The green signal input.
pin 15: GREEN 4 : IN : The green signal input.
pin 16: GREEN 5 : IN : The green signal input.
pin 17: TEST : IN : For the test.
pin 18: BLUE 0 : IN : The blue signal input.
pin 19: BLUE 1 : IN : The blue signal input.
pin 20: BLUE 2 : IN : The blue signal input.
pin 21: BLUE 3 : IN : The blue signal input.
pin 22: BLUE 4 : IN : The blue signal input.
pin 23: BLUE 5 : IN : The blue signal input.
pin 24: TEST CK : IN : The clock pulse input for the test.
pin 25: H RVE : IN : The horizontal reversing setting terminal.
pin 26: ENAB : IN : The horizontal display beginning position
setting terminal.
pin 27: VDD : - : Positive voltage supply.
pin 28: GND : - : Ground.
pin 29: TSTR : IN : The initial reset input.
pin 30: REV 1 : O : The signal output terminal for the common
electrode signal making.
pin 31: REV V 0 : O : The output terminal for the reference volt-
age making.
pin 32: GND : - : Ground.
pin 33: SPR : O : The start signal output terminal for the
source driver.
pin 34: LBR : O : The output terminal of signal that controls
the horizontal reversing display.
pin 35: SPL : O : The starting signal output to the source
driver.
DXZ955MC
DXZ956MC
Quad Bridge Audio Amplifier
L = Mute ON
L = Clipping
3 OUTPUT
2 N.C.
1 VCC
TFT LCD Controller
pin 36: LP : O : The output terminal of the data transmis-
pin 37: Clock Out : O : Clock Out.
pin 38: GND : - : Ground.
pin 39: O BLUE 5 : O : The blue signal output.
pin 40: O BLUE 4 : O : The blue signal output.
pin 41: O BLUE 3 : O : The blue signal output.
pin 42: O BLUE 2 : O : The blue signal output.
pin 43: O BLUE 1 : O : The blue signal output.
pin 44: O BLUE 0 : O : The blue signal output.
pin 45: VDD : - : Positive voltage supply.
pin 46: GND : - : Ground.
pin 47: O GREEN 5 : O : The green signal output.
pin 48: O GREEN 4 : O : The green signal output.
pin 49: O GREEN 3 : O : The green signal output.
pin 50: O GREEN 2 : O : The green signal output.
pin 51: O GREEN 1 : O : The green signal output.
pin 52: O GREEN 0 : O : The green signal output.
pin 53: GND : - : Ground.
pin 54: O RED 5 : O : The red signal output.
pin 55: O RED 4 : O : The red signal output.
pin 56: O RED 3 : O : The red signal output.
pin 57: O RED 2 : O : The red signal output.
pin 58: O RED 1 : O : The red signal output.
pin 59: O RED 0 : O : The red signal output.
pin 60: GND : - : Ground.
pin 61: CLS : O : The clock pulse output for the gate driver.
pin 62: SPS : O : The starting pulse output for the gate driv-
pin 63: VDD : - : Positive voltage supply.
pin 64: GND : - : Ground.
pin 65: UBL : O : The output terminal of signal that controls
pin 66: V RVE : IN : The vertical reversing setting terminal.
pin 67: MODE : O : The output terminal to set the gate driver's
pin 68: NU : - : Not in use.
pin 69: TEST : IN : For the test.
pin 70: REM : IN : The reset signal input terminal to make the
pin 71: HS : IN : The horizontal sync counter.
pin 72: VS : IN : The input terminal of the vertical synchro-
Table 1. The horizontal scanning setting
H RVE input SPR output
( pin 25 ) ( pin 33 )
High voltage High-Z
Low voltage start pulse
Table 2. The vertical scanning setting
V RVE input
( pin 66 )
High voltage
Low voltage
051-7107-90 TC4S81F-TE85L,F
1
2
GND 3
- 6 -
sion signal for the source driver.
er.
vertical reversing display for the gate driv-
er.
output mode.
mode signal.
nizing signal.
SPL output LBR output
( pin 35 ) ( pin 34 )
start pulse
High-Z
UBL output
( pin 65 )
H
L
Single 2-inputs AND GATE
5 VDD
4
H
L