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SECTION 4
HARDWARE COMPATIBILITY
Each DMA channel is supported by the system. Two Intel 8237-5 DMA controller chips (Four channels in
each chtp) are used. DMA channels are assigned as follows :
Channels from 0 through 3 are contained in DMA controller 1. Transfers of 8-bit data S-bit I/O adapters
and 8-bit or 16-bit system memory are supported by these channels. Each of these channels will transfer
data in 64KB blocks throughout the 6-megabyte system address space.
Channels from 4 through 7 are contained in DMA controller 2. To cascade channels 0 through 3 to the
microprocessor, use channel 1. Transfer of 16-bit data between 16-bit adapters and 16-bit system memory
are then supported by channels 5, 6, & 7. DMA channels from 5 through 7 transfer data in 128K blocks
throughout the 16-megabyte system address space.
These channels will not transfer data on odd-byte bowdaries.
The address for the page register is as follows :
Page Register
DMA channel 0
DMA channel 1
DMA channel 2
DMA channel 3
DMA channel 5
DMA channel 6
DMA channel 7
Refresh
Address generation for the DMA channels is as follows :
For DMA channels 3 through 0 :
Source
Address (
For DMA channels 7 through 5 :
Source
Address 1
Note
The BHE and A0 addressing signals are forced to a logic 0. DMA channel
addressees do not increase or decrease through page boundaries (64KB for
channels 0 through 3 and 128 KB for channels 5 through 7).
0087
0083
0081
0082
008B
0089
008A
008F
DMA Rage Registers 8237A-5
A23 .._. Al6
Al5
Al
DMA Rage Registers 8237A-5
A l 6 A0
A23 .._._ Al7
17
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