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LC32D44E/S/RU-BK/GY (1st Eddition)
14. IC8103 (VHIT3Z18AFG-1Q)
Single Link LCD Receiver
The LVDS is essentially a signaling method used for high-speed transmission of binary data over copper.
It uses a lower voltage swing than other transmission standards. This low voltage differential is what delivers higher data transmission speeds and
inherently greater bandwidth at lower power consumption.
This new technology not only addresses the needs of today's high performance data transmission application, but also the needs of future applica-
tion.
This LVDS receiver IP supports Single Link transmission between Host and Flat Panel Display. The receiver recovers the LVDS data and converts
into CMOS data. An on-chip PLL synchronizes the received clock with the parallel data and then all are transmitted to the parallel output port of the
receiver.
Description:
•
Supports Single Link (Single Input to Single Output) up to 135MHz dot clock for SXGA+ (input clock frequency: 25 to 135MHz)
•
PLL requires no external components
•
Clock strobe edge selectable
•
Support 10-bit color
•
Power down mode
Pin No.
Pin Name
1
PLLAVD
2
PLLAVS
3
VSSAGND45L
4
VDDSAVCC4
5
VSSAGND45C
6
VDDSAVCC5
7
BR0_M
8
BR0_P
9
BR1_M
10
BR1_P
11
BR2_M
12
BR2_P
13
BR3_M
14
BR3_P
15
BCLK_M
16
BCLK_P
17
VDDSAVCC4
18
VSSDGND1
19
VDDCDVCC1
20
VSSAGND45C
21
VDDSAVCC5
22
BG0_M
23
BG0_P
24
BG1_M
25
BG1_P
26
BG2_M
27
BG2_P
28
BG3_M
29
BG3_P
30
VDDSAVCC4
31
VSSDGND1
32
VDDCDVCC1
33
VSSAGND45C
34
VDDSAVCC5
35
BB0_M
36
BB0_P
37
BB1_M
38
BB1_P
39
BB2_M
40
BB2_P
41
BB3_M
42
BB3_P
43
VDDCLCDVDDC
44
VSSLCDVSS2
45
VSSAGND45R
I/O
Function Name
1.5V
E1AVDLIVC
GND
E1AVSLIVC
GND
Z7RSTAGND45L
3.3V
Z7RSTAVCC4
GND
Z7RSTAGND45C
3.3V
Z7RSTAVCC5
OUT
Z7RSDST
OUT
Z7RSDST
OUT
Z7RSDST
OUT
Z7RSDST
OUT
Z7RSDST
OUT
Z7RSDST
OUT
Z7RSDST
OUT
Z7RSDST
OUT
Z7RSDST
OUT
Z7RSDST
3.3V
Z7RSTAVCC4
GND
Z7RSTDGND1
1.5V
Z7RSTDVCC1
GND
Z7RSTAGND45C
3.3V
Z7RSTAVCC5
OUT
Z7RSDST
OUT
Z7RSDST
OUT
Z7RSDST
OUT
Z7RSDST
OUT
Z7RSDST
OUT
Z7RSDST
OUT
Z7RSDST
OUT
Z7RSDST
3.3V
Z7RSTAVCC4
GND
Z7RSTDGND1
1.5V
Z7RSTDVCC1
GND
Z7RSTAGND45C
3.3V
Z7RSTAVCC5
OUT
Z7RSDST
OUT
Z7RSDST
OUT
Z7RSDST
OUT
Z7RSDST
OUT
Z7RSDST
OUT
Z7RSDST
OUT
Z7RSDST
OUT
Z7RSDST
1.5V
Z7RSTVDDC
GND
Z7RSTVSS2
GND
Z7RSTAGND45R
Pin No.
Pin Name
141
SCLK
142
SDT
143
vext1103
144
VDDC
145
RESET
146
CMOS_IN
147
OS_SEL
148
OS_ON
149
BANK_SEL
150
TEMP[2]
151
vgnd87
152
TEMP[1]
153
TEMP[0]
154
REV_MODE
155
HSCAN
156
VSCAN
157
vext1105
158
VSS12
159
SELLVDS
160
SSCLK
161
EXCLK
162
VDDC
163
VSSAGND1L
164
RA_M
165
RA_P
166
RB_M
167
RB_P
168
RC_M
169
RC_P
170
VDDAVDD1L
171
L_VDDPLL1
172
L_VSSPLL1
173
L_VDDPLL2
174
L_VSSPLL2
175
L_VDDD
176
L_VSSD
177
PVDDA1B
178
PVDDA2B
179
VDDS_L
180
PVSSA1B
181
PVSSA2B
182
VDDC_L
183
VDDAVDD2
184
VSSAGND2
185
VDDAVDD1R
5 – 19
I/O
Function Name
OUT
BT4VIC1
I/O
BD4THVIC1
1.5V
SDRAMVDE1
1.5V
VDDC
IN
SMTCIF
IN
IBUFDIF
IN
TLCHTHDVIC1
IN
TLCHTHDVIC1
IN
TLCHTHDVIC1
IN
TLCHTHDVIC1
GND
SDRAMVSE
IN
TLCHTHDVIC1
IN
TLCHTHDVIC1
IN
TLCHTHDVIC1
IN
TLCHTHDVIC1
IN
TLCHTHDVIC1
1.5V
SDRAMVDE1
GND
VSS12
IN
TLCHTHUVIC1
I/O
BD8SCIF
IN
IBUFIF
1.5V
VDDC
GND
Z7LVRAGND1L
IN
Z7LVRXIO
IN
Z7LVRXIO
IN
Z7LVRXIO
IN
Z7LVRXIO
IN
Z7LVRXIO
IN
Z7LVRXIO
3.3V
Z7LVRAVDD1L
2.5V
Z7LVRVDDPLL1
GND
Z7LVRVSSPLL1
2.5V
Z7LVRVDDPLL2
GND
Z7LVRVSSPLL2
1.5V
Z7LVRVDDD
GND
Z7LVRVSSD
2.5V
Z7LVRVDDPLL1*1
2.5V
Z7LVRVDDPLL2*1
3.3V
Z7LVRVDDS
GND
Z7LVRVSSPLL1*1
GND
Z7LVRVSSPLL2*1
1.5V
Z7LVRVDDC
2.5V
Z7LVRAVDD2
GND
Z7LVRAGND2
3.3V
Z7LVRAVDD1R
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