Major Ic Informations; Ic207 (Rh-Ixb964Wjzzq); Chapter 5. Major Ic Informations - Sharp LC-32D44E Service Manual

LC32D44E/S/RU-BK/GY (1st Eddition)
LC32D44E-BK
CHAPTER 5.

MAJOR IC INFORMATIONS

[1] MAJOR IC INFORMATIONS

1. IC207 (RH-iXB964WJZZQ)

The STv0362 is a single-chip demodulator using COFDM (coded orthogonal frequency division Multiplexing) and is intended for digital terrestrial
receivers using compressed video, sound and data services. It converts IF or base band differential signals to MPEG-2 format by processing OFDM
carriers.
The STv0362 is fully compliant with the DVB-T specification (ETS 300 744) and Nor Dig Unified specification.
Pin No.
Clock and resets
32
15
14
13
16
Analog interface
1
2
3
4
5
6
7
8
9
10
11
12
I2C interface
29
30
21
20
MPEG interface
43
42
40
39
37
36
35
33
44
46
47
48
Front end controls
18
17
64
27
49
60
59
58
57
54
53
52
61
23
25
Pin Name I/O
NOT_RESET I Hardware reset, active low
XTAL_I I Analog Crystal oscillator input/external clock (2.5 V)
XTAL_O O Analog Crystal oscillator output
VDDA_2V5 --- Supply Analog oscillator supply (2.5 V)
VDDA_2V5 --- Supply Analog PLL supply (2.5 V)
RF_LEVEL --- ADC 8 input for RF level monitoring
VDDA_2V5 --- Analog ADC 8 supply (2.5 V)
QP --- Positive Q analog input for baseband configuration
QM --- Negative Q analog input for baseband configuration
VDDA_ISO --- Analog ISO nwell polarization (2.5 V)
VDDA_2V5 --- Analog ADC 12 supply (2.5 V)
REFP --- Internal positive reference
REFM --- Internal negative reference
INCM --- Internal common mode
IM --- Negative I analog input for IF and baseband configuration
IP --- Positive I analog input for IF and baseband configuration
VDDA_1.0 --- Analog supply (1.0 V)
SDA I/O Serial data (open drain)
SCL I Serial clock (open drain)
SDAT I/O SDA tuner (open drain)
SCLT I SCL tuner
D7 O Serial MPEG data or parallel MPEG data (bit 7)
D6 O Parallel MPEG data (bit 6)
D5 O Parallel MPEG data (bit 5)
D4 O Parallel MPEG data (bit 4)
D3 O Parallel MPEG data (bit 3)
D2 O Parallel MPEG data (bit 2)
D1 O Parallel MPEG data (bit 1)
D0 O Parallel MPEG data (bit 0)
CLK_OUT O MPEG byte or bit clock
STR_OUT O MPEG first byte sync
D/NOT_P O MPEG data valid/parity
ERROR O MPEG packet error
AGC_RF I/O RF AGC control
AGC_IF I/O
IF AGC control
TEST I/O Reserved test mode, must be grounded.
GPIO0 I/O General-purpose input/output port 0. Reserved test mode, must be grounded.
GPIO1 I/O General-purpose input/output port 1
GPIO2 I/O General-purpose input/output port 2 or lock indicator
GPIO3 I/O General-purpose input/output port 3 or lock indicator
GPIO4 I/O General-purpose input/output port 4
GPIO5 I/O General-purpose input/output port 5
GPIO6 I/O General-purpose input/output port 6
GPIO7 I/O General-purpose input/output port 7
GPIO8 I/O General-purpose input/output port 8. Reserved test mode, must be grounded.
GPIO9 I/O General-purpose input/output port 9
AUX_CLK I/O Auxiliary clock
CS0 I Chip select LSB
5 – 1
Service Manual
Pin Function
(5 V tolerant)
(5 V tolerant)