Sony DP-IF8000 Service Manual page 7

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• MICON-DECODER period
Check the DEC_XCS (IC11-2pin), SCK1 (IC11-1pin), SDO1 (IC11-
143pin), SDI1 (IC11-144pin).
Figure 19 shows the view on the monitor after power is turned on,
at the instant of switching with the OUTPUT key. The timing is
shown in detail in FIG. 20.
DEC_XCS
SCK 1
SDO 1
SDI 1
DEC_XCS
SCK 1
(1MHz)
SDO 1
SDI 1
• MICON-MAIN DSP period
Check the DSP_XCS (IC19-2pin), SCK1 (IC19-1pin), SDO1 (IC19-
143pin), and the DSP_XHREQ (IC19-3pin).
Figure 21 shows the view on the monitor after power is turned on,
at the instant of switching with the OUTPUT key. (The detailed
timing is the shown as shown in FIG. 20.
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L 13942296513
DSP_XCS
SCK 1
(1MHz)
SDO 1
DSP_XHREQ
Start of 24 bit data transfer, at 2nd bit, HREQ t 1
After transfer of 24 bit data, HREQ t 0
2.2 Headphones
2.2.1 Audio System
Note: Switch to Digital Input mode by connecting the optical cable
to DIGITAL IN 1 or 2, and pressing the INPUT key.
• Master clock
DSP_MCK(IC501-34pin) : 12.288 MHz (fixed)
DAC_MCK (IC102-2pin) : 12.288 MHz when the input source sam-
pling frequency to the processor is 48 kHz.
11.289 MHz when the sampling frequency is 44.1 kHz
8.192 MHz when the sampling frequency is 32 kHz
• DIAT-DSP period
Check the LRCK/RCS (IC501-94pin), BCK (IC501-6pin),
DIAT_OUT (IC501-20pin), RINFO (IC501-19pin).
Turn the power on, set in Digital Input mode, and select VIRTUAL
FRONT, or VIRTUAL 5.1 or VIRTUAL 6.1 with the OUTPUT
key.
Turn the headphone power on.
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The view on the monitor when the input source sampling frequency
to the processor is 48 kHz is shown in Fig. 22.
The view on the monitor when the input source sampling frequency
to the processor is 44.1 kHz is shown in Fig. 23.
.
The view on the monitor when the input source sampling frequency
to the processor is 32 kHz is shown in Fig. 24.
The view on the monitor when OFF is selected with the OUTPUT
key is shown in Fig. 25. The detailed timing is shown in Fig. 26.
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Sending the Receiving the
24 bit data 24 bit data (example)
Fig 19
Fig 20
Fig 21
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8
LRCK/RCS
BCK
DIAT_OUT
RINFO
Note 7: fs=48kHz
LRCK/RCS
BCK
DIAT_OUT
RINFO
Note 8: fs=44.1kHz
LRCK/RCS
BCK
DIAT_OUT
RINFO
Note 9: fs=32kHz
LRCK/RCS
BCK
Q Q
3 6 7 1 3 1 5
DIAT_OUT
RINFO
Note 10: Only LRCK, BCK and DATA are enabled. RINFO
is disabled.
LRCK/RCS
BCK
DIAT_OUT
RINFO
• DSP-DAC period
Check the LRCK (IC102-16pin), BCK (IC102-14pin), and
DSP_OUT (IC102-15pin).
Turn on the processor and set to Digital Input mode. Turn on the
headphone power, and apply an input source signal (any kind is
okay) to the processor.
The view on the monitor is shown in Fig. 27, and the detailed tim-
ing is shown in Fig. 28.
LRCK
BCK
DSP_OUT
co
LRCK
BCK
.
DSP_OUT
1 bit offset (I
DP-IF8000
9 4 2 8
0001000 t fs=48k
Fig 22
0000000 t fs=44.1k
Fig 23
0011000 t fs=32k
Fig 24
Lch
0 5 8 2 9 9 4 2 8
Fig 25
Fig 26
Lch Rch
m
Fig 27
S format)
2
Fig 28
9 9
Rch
9 9
7